blob: e49d7e4e9f9211441a8b92c4e2eff5b52ef38faa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef _SYNCDELAY_H_
#define _SYNCDELAY_H_
/*
* Magic delay required between access to certain xdata registers (TRM page 15-106).
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
* NOP is a single cycle....
*
* From TRM page 15-105:
*
* Under certain conditions, some read and write access to the FX2 registers must
* be separated by a "synchronization delay". The delay is necessary only under the
* following conditions:
*
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
* of the registers listed below.
*
* - between a write to one of the registers listed below and a read from any register
* in the 0xE600 - 0xE6FF range.
*
* Registers which require a synchronization delay:
*
* FIFORESET FIFOPINPOLAR
* INPKTEND EPxBCH:L
* EPxFIFOPFH:L EPxAUTOINLENH:L
* EPxFIFOCFG EPxGPIFFLGSEL
* PINFLAGSAB PINFLAGSCD
* EPxFIFOIE EPxFIFOIRQ
* GPIFIE GPIFIRQ
* UDMACRCH:L GPIFADRH:L
* GPIFTRIG EPxGPIFTRIG
* OUTPKTEND REVCTL
* GPIFTCB3 GPIFTCB2
* GPIFTCB1 GPIFTCB0
*/
/*
* FIXME ensure that the peep hole optimizer isn't screwing us
*/
#define SYNCDELAY _asm nop; nop; nop; _endasm
#define NOP _asm nop; _endasm
#endif /* _SYNCDELAY_H_ */
|
