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path: root/usrp2/fpga
AgeCommit message (Expand)Author
2009-10-01Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan
2009-10-01Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus
2009-10-01fullchip sim now compiles again, after moving eth and models over to new simp...Matt Ettus
2009-10-01remove unused opencoresMatt Ettus
2009-09-30Merge branch 'new_wb_intercon' into new_ethMatt Ettus
2009-09-30no idea where this came from, it shouldn't be hereMatt Ettus
2009-09-30Copied wb_1master back from quad radioMatt Ettus
2009-09-29Enable pps interrupts. Not sure why they were disabled in the first place.Matt Ettus
2009-09-24Merge commit 'origin' into new_ethMatt Ettus
2009-09-24Synchronize the internal phase of the halfband filters to theMatt Ettus
2009-09-20Merge branch 'serdes_newfifo' into new_ethMatt Ettus
2009-09-10Remove old mac. Good riddance.Matt Ettus
2009-09-10remove unused portMatt Ettus
2009-09-10More xilinx fifos, more clean up of our fifosMatt Ettus
2009-09-10might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus
2009-09-05fix a typo which caused tx glitchesMatt Ettus
2009-09-04Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus
2009-09-04Implement Eth flow control using pause framesMatt Ettus
2009-09-04parameterized fifo sizes, some reformattingMatt Ettus
2009-09-04remove unused old style fifoMatt Ettus
2009-09-04allow control of whether or not to honor flow control, adds some debug linesMatt Ettus
2009-09-04debug the rx sideMatt Ettus
2009-09-04no longer used, replaced by newfifo versionMatt Ettus
2009-09-03seems to build a decent fpga, but still some issues with a full connection.Matt Ettus
2009-09-03MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus
2009-09-03set device to xc3s2000. Shouldn't make any differences.Matt Ettus
2009-09-03misc ignoresMatt Ettus
2009-09-03made a new block ram based fifo, 64 (65) elements long, all fifos now have "e...Matt Ettus
2009-09-02bring the testbench files up to dateMatt Ettus
2009-09-02major cleanup of 2 clock fifosMatt Ettus
2009-09-02cleaning up the new fifosMatt Ettus
2009-09-02cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an...Matt Ettus
2009-09-02never used, not neededMatt Ettus
2009-09-02debug pins, cleaned ignoresMatt Ettus
2009-09-02sort out active-low lines on locallink fifos, added debug pinsMatt Ettus
2009-09-02Removed these files completely, they were for the old style of fifosMatt Ettus
2009-09-01fixed addressing of registers, and added write enables to those that were mis...Matt Ettus
2009-08-31Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan
2009-08-14Added git ignore files auto created from svn:ignore properties.git
2009-07-30Add custom FPGA build.jcorgan
2009-04-27Fix swapped signals.jcorgan
2009-04-22Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG...jcorgan
2009-04-12mostly formatting and name changes. commented out special purpose pins.matt
2009-04-12from u2p2, autogeneratedmatt
2009-04-06now handles odd length packetsmatt
2009-04-04basic wrapper workingmatt
2009-04-04Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea...jcorgan
2009-04-04first cut at a wishbone interface and wrapping the corematt
2009-04-04copied over from other eth corematt
2009-04-04reset synchronizermatt