| Age | Commit message (Expand) | Author |
|---|
| 2009-09-10 | remove unused port | Matt Ettus |
| 2009-09-10 | More xilinx fifos, more clean up of our fifos | Matt Ettus |
| 2009-09-10 | might as well use a cascade fifo to help timing and give a little more capacity | Matt Ettus |
| 2009-09-05 | fix a typo which caused tx glitches | Matt Ettus |
| 2009-09-04 | Implement Eth flow control using pause frames | Matt Ettus |
| 2009-09-04 | parameterized fifo sizes, some reformatting | Matt Ettus |
| 2009-09-04 | remove unused old style fifo | Matt Ettus |
| 2009-09-04 | allow control of whether or not to honor flow control, adds some debug lines | Matt Ettus |
| 2009-09-04 | debug the rx side | Matt Ettus |
| 2009-09-04 | no longer used, replaced by newfifo version | Matt Ettus |
| 2009-09-03 | seems to build a decent fpga, but still some issues with a full connection. | Matt Ettus |
| 2009-09-03 | MAC transmit seems to work now. The root cause of the problem was accidental... | Matt Ettus |
| 2009-09-03 | set device to xc3s2000. Shouldn't make any differences. | Matt Ettus |
| 2009-09-03 | misc ignores | Matt Ettus |
| 2009-09-03 | made a new block ram based fifo, 64 (65) elements long, all fifos now have "e... | Matt Ettus |
| 2009-09-02 | bring the testbench files up to date | Matt Ettus |
| 2009-09-02 | major cleanup of 2 clock fifos | Matt Ettus |
| 2009-09-02 | cleaning up the new fifos | Matt Ettus |
| 2009-09-02 | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an... | Matt Ettus |
| 2009-09-02 | never used, not needed | Matt Ettus |
| 2009-09-02 | debug pins, cleaned ignores | Matt Ettus |
| 2009-09-02 | sort out active-low lines on locallink fifos, added debug pins | Matt Ettus |
| 2009-09-02 | Removed these files completely, they were for the old style of fifos | Matt Ettus |
| 2009-09-01 | fixed addressing of registers, and added write enables to those that were mis... | Matt Ettus |
| 2009-08-31 | Merged SVN matt/new_eth r10782:11633 into new_eth | Johnathan Corgan |
| 2009-08-14 | Added git ignore files auto created from svn:ignore properties. | git |
| 2009-07-30 | Add custom FPGA build. | jcorgan |
| 2009-04-27 | Fix swapped signals. | jcorgan |
| 2009-04-22 | Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG... | jcorgan |
| 2009-04-12 | mostly formatting and name changes. commented out special purpose pins. | matt |
| 2009-04-12 | from u2p2, autogenerated | matt |
| 2009-04-06 | now handles odd length packets | matt |
| 2009-04-04 | basic wrapper working | matt |
| 2009-04-04 | Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea... | jcorgan |
| 2009-04-04 | first cut at a wishbone interface and wrapping the core | matt |
| 2009-04-04 | copied over from other eth core | matt |
| 2009-04-04 | reset synchronizer | matt |
| 2009-04-03 | made pause enabling a pin so we can set it | matt |
| 2009-04-02 | Properly signals an error and drops the remainder of the packet if there is a... | matt |
| 2009-04-02 | more thorough tests, including overrun, underrun, crc err, etc. | matt |
| 2009-04-02 | simulate a hiccup in the filling of the fifo. If long enough, will cause a t... | matt |
| 2009-04-02 | debug ports for fifo level testing. Normally I wouldn't check this in, but a... | matt |
| 2009-04-02 | Fix for fifo overruns on eth rx in full duplex. Now send re-pause long befor... | matt |
| 2009-04-02 | test multiple error types | matt |
| 2009-04-02 | added a state to ensure the error signal propagates, and now we assert src_rd... | matt |
| 2009-04-02 | only write one error into fifo | matt |
| 2009-04-02 | generate error signal | matt |
| 2009-04-02 | added error output line, alternative to simultaneous sof/eof | matt |
| 2009-04-02 | logic to interface locallink fifos to our mac | matt |
| 2009-04-01 | add fifos to interface to the macs | matt |
