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AgeCommit message (Collapse)Author
2009-10-11earliest beta files renamed to avoid confusionMatt Ettus
2009-10-05Properly reset the fifos. We didn't connect before.Matt Ettus
2009-10-01Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
2009-10-01Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus
2009-10-01fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus
simple_gemac
2009-10-01remove unused opencoresMatt Ettus
2009-09-30Merge branch 'new_wb_intercon' into new_ethMatt Ettus
Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
2009-09-30no idea where this came from, it shouldn't be hereMatt Ettus
2009-09-30Copied wb_1master back from quad radioMatt Ettus
more sane config options, should be exactly the same memory map
2009-09-29Enable pps interrupts. Not sure why they were disabled in the first place.Matt Ettus
2009-09-24Merge commit 'origin' into new_ethMatt Ettus
Conflicts: .gitignore
2009-09-24Synchronize the internal phase of the halfband filters to theMatt Ettus
start of the "run" signal. This is important for MIMO. Bug reported by Christoph Hein and Hanwen .
2009-09-20Merge branch 'serdes_newfifo' into new_ethMatt Ettus
2009-09-10Remove old mac. Good riddance.Matt Ettus
2009-09-10remove unused portMatt Ettus
2009-09-10More xilinx fifos, more clean up of our fifosMatt Ettus
2009-09-10might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus
2009-09-05fix a typo which caused tx glitchesMatt Ettus
2009-09-04Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus
2009-09-04Implement Eth flow control using pause framesMatt Ettus
Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
2009-09-04parameterized fifo sizes, some reformattingMatt Ettus
2009-09-04remove unused old style fifoMatt Ettus
2009-09-04allow control of whether or not to honor flow control, adds some debug linesMatt Ettus
2009-09-04debug the rx sideMatt Ettus
2009-09-04no longer used, replaced by newfifo versionMatt Ettus
2009-09-03seems to build a decent fpga, but still some issues with a full connection.Matt Ettus
2009-09-03MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus
accidentally using the rx_clk in one stage of the fifos on the tx side.
2009-09-03set device to xc3s2000. Shouldn't make any differences.Matt Ettus
2009-09-03misc ignoresMatt Ettus
2009-09-03made a new block ram based fifo, 64 (65) elements long, all fifos now have ↵Matt Ettus
"enhanced level logic" for accurate fullness. Maybe this will help...
2009-09-02bring the testbench files up to dateMatt Ettus
2009-09-02major cleanup of 2 clock fifosMatt Ettus
2009-09-02cleaning up the new fifosMatt Ettus
2009-09-02cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v ↵Matt Ettus
and fifo_2clock.v are empty
2009-09-02never used, not neededMatt Ettus
2009-09-02debug pins, cleaned ignoresMatt Ettus
2009-09-02sort out active-low lines on locallink fifos, added debug pinsMatt Ettus
2009-09-02Removed these files completely, they were for the old style of fifosMatt Ettus
2009-09-01fixed addressing of registers, and added write enables to those that were ↵Matt Ettus
missing. MDIO seems ok.
2009-08-31Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
2009-08-14Added git ignore files auto created from svn:ignore properties.git
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11592 221aa14e-8319-0410-a670-987f0aec2ac5
2009-07-30Add custom FPGA build.jcorgan
This is a custom build for USRP2 FPGA. It allows using a BasicRX or LFRX board and feed two independent, real signals. In addition, instead of the CIC/HB decimator, which optimizes frequency response, it uses an integrate and dump decimator, which optimizes for time-domain impulse response. These changes have been made in dsp_core_rx.v: * A second DDC has been added, sharing a frequency register with the existing DDC. * The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... into the receive FIFO. This limits the host configured decimation to 8 intead of 4. Use gr.deinterleave to recover the streams. * The ADCs are hardcoded: RX_A ==> DDC #1 I-input 0 ==> DDC #1 Q-input RX_B ==> DDC #2 I-input 0 ==> DDC #2 Q-input Thus, the input mux has been disabled. * The CIC/HB decimator has been replaced by an integrate and dump at the decimation rate. * To assist with meeting timing, the external RAM has been disabled. The basic application is to coherently sample two real IF streams and downconvert to baseband, while minimizing the impulse response duration of the resampling filters. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11519 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-27Fix swapped signals.jcorgan
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10926 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-22Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 ↵jcorgan
FPGA build to use integrate-and-dump decimator instead of CIC/HB combination. This provides a much shorter time duration impulse response for the same decimation rate, at the expense of worse stop-band rejection. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10888 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-12mostly formatting and name changes. commented out special purpose pins.matt
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10814 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-12from u2p2, autogeneratedmatt
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10813 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-06now handles odd length packetsmatt
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10779 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-04basic wrapper workingmatt
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10769 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-04Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and ↵jcorgan
streaming GPIO functions for USRP2. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10766 221aa14e-8319-0410-a670-987f0aec2ac5
2009-04-04first cut at a wishbone interface and wrapping the corematt
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10762 221aa14e-8319-0410-a670-987f0aec2ac5
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