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| author | Matt Ettus | 2009-10-05 02:15:10 -0700 |
|---|---|---|
| committer | Matt Ettus | 2009-10-05 02:15:10 -0700 |
| commit | 61926130bef20051001f97abfae4c16ffc7963f6 (patch) | |
| tree | d59579154742a6cd7f807696e3712c633ad52a57 /usrp2/fpga | |
| parent | bf76534044a1bbcc665f0400a53d1070cae8caf0 (diff) | |
| download | gnuradio-61926130bef20051001f97abfae4c16ffc7963f6.tar.gz gnuradio-61926130bef20051001f97abfae4c16ffc7963f6.tar.bz2 gnuradio-61926130bef20051001f97abfae4c16ffc7963f6.zip | |
Properly reset the fifos. We didn't connect before.
Diffstat (limited to 'usrp2/fpga')
| -rw-r--r-- | usrp2/fpga/control_lib/newfifo/fifo_2clock.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v index 07ae090f2..34c85ccb4 100644 --- a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v +++ b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v @@ -19,28 +19,28 @@ module fifo_2clock if(WIDTH==36) if(SIZE==9) fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==11) fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==6) fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if((WIDTH==19)|(WIDTH==18)) if(SIZE==4) fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate |