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path: root/usrp2/fpga/control_lib
AgeCommit message (Expand)Author
2009-10-05Properly reset the fifos. We didn't connect before.Matt Ettus
2009-09-30Merge branch 'new_wb_intercon' into new_ethMatt Ettus
2009-09-30Copied wb_1master back from quad radioMatt Ettus
2009-09-10More xilinx fifos, more clean up of our fifosMatt Ettus
2009-09-04remove unused old style fifoMatt Ettus
2009-09-04no longer used, replaced by newfifo versionMatt Ettus
2009-09-03MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus
2009-09-02bring the testbench files up to dateMatt Ettus
2009-09-02major cleanup of 2 clock fifosMatt Ettus
2009-09-02cleaning up the new fifosMatt Ettus
2009-09-02cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an...Matt Ettus
2009-09-02never used, not neededMatt Ettus
2009-09-02Removed these files completely, they were for the old style of fifosMatt Ettus
2009-08-31Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan
2009-08-14Added git ignore files auto created from svn:ignore properties.git
2009-04-06now handles odd length packetsmatt
2009-04-04reset synchronizermatt
2009-03-30copied over from other projectmatt
2009-03-30new fifos copied over from other projectmatt
2009-02-26timing fix. The line address in the buffers still updates now even if there ...matt
2009-01-31work in progressmatt
2009-01-31work in progressmatt
2008-12-04speed up the diagnostic signals, they were causing timing problemsmatt
2008-10-11New serdes status interrupt, clk_status interrupt. New capability to flush t...matt
2008-10-08moved to appropriate placesmatt
2008-09-21attach a 16 bit device to the bus and make it look like a 32 bit devicematt
2008-09-17control CS line on SD cardmatt
2008-09-08Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2...jcorgan
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