diff options
Diffstat (limited to 'usrp2/fpga/top/u2_rev3')
| -rw-r--r-- | usrp2/fpga/top/u2_rev3/Makefile | 2 | ||||
| -rw-r--r-- | usrp2/fpga/top/u2_rev3/u2_rev3.v | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile index 897b68d68..e023eb1a4 100644 --- a/usrp2/fpga/top/u2_rev3/Makefile +++ b/usrp2/fpga/top/u2_rev3/Makefile @@ -87,6 +87,8 @@ control_lib/simple_uart.v \ control_lib/simple_uart_tx.v \ control_lib/simple_uart_rx.v \ control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ coregen/fifo_xlnx_2Kx36_2clk.v \ coregen/fifo_xlnx_2Kx36_2clk.xco \ coregen/fifo_xlnx_512x36_2clk.v \ diff --git a/usrp2/fpga/top/u2_rev3/u2_rev3.v b/usrp2/fpga/top/u2_rev3/u2_rev3.v index c1a81a961..db34b2dc3 100644 --- a/usrp2/fpga/top/u2_rev3/u2_rev3.v +++ b/usrp2/fpga/top/u2_rev3/u2_rev3.v @@ -162,8 +162,10 @@ module u2_rev3 // reset the watchdog continuously reg [15:0] wd; + wire config_success; + always @(posedge wb_clk) - if(POR) + if(~config_success) wd <= 0; else wd <= wd + 1; @@ -375,6 +377,10 @@ module u2_rev3 .cpld_din (cpld_din), .cpld_clk (cpld_clk), .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), .adc_a (adc_a_reg2), .adc_ovf_a (adc_ovf_a_reg2), .adc_on_a (adc_on_a), |