diff options
Diffstat (limited to 'usrp2/fpga/testbench')
| -rw-r--r-- | usrp2/fpga/testbench/BOOTSTRAP.sav | 82 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/Makefile | 10 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/PAUSE.sav | 62 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/README | 5 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/SERDES.sav | 35 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/U2_SIM.sav | 95 | ||||
| -rw-r--r-- | usrp2/fpga/testbench/cmdfile | 39 |
7 files changed, 328 insertions, 0 deletions
diff --git a/usrp2/fpga/testbench/BOOTSTRAP.sav b/usrp2/fpga/testbench/BOOTSTRAP.sav new file mode 100644 index 000000000..41501945f --- /dev/null +++ b/usrp2/fpga/testbench/BOOTSTRAP.sav @@ -0,0 +1,82 @@ +[size] 1400 971 +[pos] -1 -1 +*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +u2_sim_top.cpld_clk +u2_sim_top.cpld_detached +u2_sim_top.cpld_din +u2_sim_top.cpld_done +u2_sim_top.cpld_start +u2_sim_top.aux_clk +u2_sim_top.clk_fpga +u2_sim_top.clk_sel[1:0] +u2_sim_top.clk_en[1:0] +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.sysctrl.ram_loader_done_i +u2_sim_top.cpld_model.sclk +u2_sim_top.cpld_model.start +u2_sim_top.u2_basic.ram_loader.rst_i +u2_sim_top.sen_clk +u2_sim_top.sen_dac +u2_sim_top.sclk +@22 +u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] +u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] +@28 +u2_sim_top.u2_basic.shared_spi.wb_we_i +u2_sim_top.u2_basic.shared_spi.wb_stb_i +u2_sim_top.u2_basic.shared_spi.wb_ack_o +@22 +u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] +u2_sim_top.u2_basic.shared_spi.ctrl[13:0] +u2_sim_top.u2_basic.shared_spi.divider[15:0] +u2_sim_top.u2_basic.shared_spi.char_len[6:0] +u2_sim_top.u2_basic.shared_spi.ss[7:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] +u2_sim_top.u2_basic.shared_spi.rx[127:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_stb_i +u2_sim_top.u2_basic.control_lines.wb_we_i +@22 +u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] +u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_cyc_i +@22 +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.clock_ready +u2_sim_top.u2_basic.ram_loader.done_o +u2_sim_top.u2_basic.dsp_rst +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +@22 +u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] +@28 +u2_sim_top.u2_basic.aeMB.iwb_ack_i +u2_sim_top.u2_basic.ram_loader_done +@22 +u2_sim_top.u2_basic.iram_rd_adr[15:0] +u2_sim_top.u2_basic.iram_rd_dat[31:0] +@28 +u2_sim_top.u2_basic.iram_wr_we +u2_sim_top.u2_basic.iram_wr_stb +@22 +u2_sim_top.u2_basic.iram_wr_sel[3:0] +u2_sim_top.u2_basic.iram_wr_dat[31:0] +u2_sim_top.u2_basic.iram_wr_adr[15:0] +@28 +u2_sim_top.u2_basic.ram_loader.ram_loader_done_o +u2_sim_top.u2_basic.ID_ram.dwb_we_i +u2_sim_top.u2_basic.ID_ram.iwb_we_i +u2_sim_top.u2_basic.ram_loader.ram_we +u2_sim_top.u2_basic.ram_loader.ram_we_q +u2_sim_top.u2_basic.ram_loader.ram_we_s +u2_sim_top.u2_basic.ram_loader.wb_ack_i +u2_sim_top.u2_basic.ID_ram.iwb_ack_o +u2_sim_top.u2_basic.ID_ram.iwb_stb_i +u2_sim_top.u2_basic.ID_ram.wb_rst_i diff --git a/usrp2/fpga/testbench/Makefile b/usrp2/fpga/testbench/Makefile new file mode 100644 index 000000000..6032a0123 --- /dev/null +++ b/usrp2/fpga/testbench/Makefile @@ -0,0 +1,10 @@ +all: single dual + +single: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim + +dual: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim + +clean: + rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/usrp2/fpga/testbench/PAUSE.sav b/usrp2/fpga/testbench/PAUSE.sav new file mode 100644 index 000000000..f5e1ea1ac --- /dev/null +++ b/usrp2/fpga/testbench/PAUSE.sav @@ -0,0 +1,62 @@ +[size] 1400 967 +[pos] -1 -1 +*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] u2_sim_top. +[treeopen] u2_sim_top.u2_basic. +[treeopen] u2_sim_top.u2_basic.MAC_top. +[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. +@22 +u2_sim_top.GMII_TXD[7:0] +@28 +u2_sim_top.GMII_TX_EN +@200 +- +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en +u2_sim_top.u2_basic.proc_int +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@25 +u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] diff --git a/usrp2/fpga/testbench/README b/usrp2/fpga/testbench/README new file mode 100644 index 000000000..14bbb68bb --- /dev/null +++ b/usrp2/fpga/testbench/README @@ -0,0 +1,5 @@ +The path to happiness: + +make clean +make +./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/usrp2/fpga/testbench/SERDES.sav b/usrp2/fpga/testbench/SERDES.sav new file mode 100644 index 000000000..3bb6ba929 --- /dev/null +++ b/usrp2/fpga/testbench/SERDES.sav @@ -0,0 +1,35 @@ +[size] 1400 967 +[pos] -1 -1 +*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] u2_sim_top. +[treeopen] u2_sim_top.u2_basic. +[treeopen] u2_sim_top.u2_basic.serdes. +@22 +u2_sim_top.u2_basic.serdes.ser_t[15:0] +@28 +u2_sim_top.u2_basic.serdes.ser_tklsb +u2_sim_top.u2_basic.serdes.ser_tkmsb +u2_sim_top.u2_basic.ram_loader.ram_loader_done_o +u2_sim_top.u2_basic.proc_int +@22 +u2_sim_top.u2_basic.serdes.fifo_space[15:0] +@28 +u2_sim_top.u2_basic.serdes.inhibit_tx +u2_sim_top.u2_basic.serdes.send_xoff +u2_sim_top.u2_basic.serdes.send_xon +u2_sim_top.u2_basic.serdes.sent +u2_sim_top.u2_basic.serdes.xoff_rcvd +u2_sim_top.u2_basic.serdes.xon_rcvd +u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o +u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o +u2_sim_top.u2_basic.serdes.serdes_rx.write +@22 +u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0] +@28 +(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +@22 +#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +u2_sim_top.u2_basic.serdes.ser_t[15:0] +@28 +u2_sim_top.u2_basic.serdes.ser_tklsb diff --git a/usrp2/fpga/testbench/U2_SIM.sav b/usrp2/fpga/testbench/U2_SIM.sav new file mode 100644 index 000000000..d320c2b6c --- /dev/null +++ b/usrp2/fpga/testbench/U2_SIM.sav @@ -0,0 +1,95 @@ +[size] 1400 971 +[pos] -1 -1 +*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +u2_sim_top.adc_oen_a +u2_sim_top.adc_oen_b +u2_sim_top.adc_pdn_a +u2_sim_top.adc_pdn_b +u2_sim_top.aux_clk +u2_sim_top.POR +u2_sim_top.clk_fpga +u2_sim_top.clk_en[1:0] +u2_sim_top.clk_sel[1:0] +u2_sim_top.led1 +u2_sim_top.led2 +u2_sim_top.sclk +u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0] +u2_sim_top.sda_pad_o +u2_sim_top.sda_pad_oen_o +u2_sim_top.sdi +u2_sim_top.sdo +u2_sim_top.sen_clk +u2_sim_top.sen_dac +u2_sim_top.ser_enable +u2_sim_top.ser_loopen +u2_sim_top.ser_prbsen +u2_sim_top.ser_rx_en +u2_sim_top.u2_basic.sysctrl.start +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.done +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.sysctrl.aux_clk +u2_sim_top.u2_basic.sysctrl.clk_fpga +u2_sim_top.u2_basic.sysctrl.done +u2_sim_top.u2_basic.bus_writer.start +u2_sim_top.u2_basic.bus_writer.done +@22 +u2_sim_top.u2_basic.bus_writer.rom_addr[15:0] +u2_sim_top.u2_basic.bus_writer.rom_data[47:0] +u2_sim_top.u2_basic.bus_writer.state[3:0] +@29 +u2_sim_top.u2_basic.bus_writer.wb_ack_i +@22 +u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0] +@28 +u2_sim_top.u2_basic.bus_writer.wb_clk_i +u2_sim_top.u2_basic.bus_writer.wb_cyc_o +@22 +u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0] +u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0] +@28 +u2_sim_top.u2_basic.bus_writer.wb_stb_o +u2_sim_top.u2_basic.bus_writer.wb_we_o +u2_sim_top.u2_basic.bus_writer.wb_rst_i +u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0] +u2_sim_top.sda_pad_i +u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i +u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o +@22 +u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0] +u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0] +@28 +u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i +u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i +u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i +u2_sim_top.u2_basic.control_lines.wb_cyc_i +u2_sim_top.u2_basic.control_lines.wb_stb_i +u2_sim_top.u2_basic.control_lines.wb_we_i +u2_sim_top.u2_basic.control_lines.wb_ack_o +u2_sim_top.u2_basic.s0_ack +@22 +u2_sim_top.u2_basic.control_lines.internal_reg[31:0] +u2_sim_top.u2_basic.control_lines.port_output[31:0] +@28 +u2_sim_top.u2_basic.led1 +u2_sim_top.u2_basic.led2 +@22 +u2_sim_top.u2_basic.misc_outs[7:0] +u2_sim_top.u2_basic.clock_outs[7:0] +u2_sim_top.u2_basic.adc_outs[7:0] +u2_sim_top.u2_basic.serdes_outs[7:0] +@28 +u2_sim_top.u2_basic.shared_spi.miso_pad_i +u2_sim_top.u2_basic.shared_spi.mosi_pad_o +@22 +u2_sim_top.u2_basic.shared_spi.ss[7:0] +u2_sim_top.u2_basic.shared_spi.divider[15:0] +@28 +u2_sim_top.u2_basic.shared_spi.sclk_pad_o +@22 +u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile new file mode 100644 index 000000000..d55567f7e --- /dev/null +++ b/usrp2/fpga/testbench/cmdfile @@ -0,0 +1,39 @@ + +# My stuff +-y . +-y ../top/u2_core +-y ../control_lib +-y ../serdes +-y ../sdr_lib +-y ../timing +-y ../coregen + +# Models +-y ../models +-y ../models/CY7C1356C + +# Open Cores +-y ../opencores/8b10b +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/wb_conbus/rtl/verilog ++incdir+../opencores/wb_conbus/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_pic/rtl + +# Ethernet ++incdir+../eth/rtl/verilog +-y ../eth/rtl/verilog +-y ../eth/rtl/verilog/MAC_tx +-y ../eth/rtl/verilog/MAC_rx +-y ../eth/rtl/verilog/miim +-y ../eth/rtl/verilog/TECH +-y ../eth/rtl/verilog/TECH/xilinx +-y ../eth/rtl/verilog/RMON +-y ../eth +-y ../eth/bench/verilog + +# Ethernet Models +-y ../eth/bench/verilog |