diff options
Diffstat (limited to 'usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v')
| -rw-r--r-- | usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v | 128 |
1 files changed, 0 insertions, 128 deletions
diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v deleted file mode 100644 index d6bb22b51..000000000 --- a/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v +++ /dev/null @@ -1,128 +0,0 @@ -//////////////////////////////////////////////////////////////////////
-//// ////
-//// CRC_chk.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (gaojon@yahoo.com) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: CRC_chk.v,v $
-// Revision 1.3 2006/01/19 14:07:54 maverickist
-// verification is complete.
-//
-// Revision 1.2 2005/12/16 06:44:16 Administrator
-// replaced tab with space.
-// passed 9.6k length frame test.
-//
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
-// no message
-//
-
-module CRC_chk(
-Reset ,
-Clk ,
-CRC_data ,
-CRC_init ,
-CRC_en ,
-//From CPU
-CRC_chk_en ,
-CRC_err
-);
-input Reset ;
-input Clk ;
-input[7:0] CRC_data ;
-input CRC_init ;
-input CRC_en ;
- //From CPU
-input CRC_chk_en ;
-output CRC_err ;
-//******************************************************************************
-//internal signals
-//******************************************************************************
-reg [31:0] CRC_reg;
-//******************************************************************************
-//input data width is 8bit, and the first bit is bit[0]
-function[31:0] NextCRC;
- input[7:0] D;
- input[31:0] C;
- reg[31:0] NewCRC;
- begin
- NewCRC[0]=C[24]^C[30]^D[1]^D[7];
- NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
- NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
- NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
- NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
- NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
- NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
- NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
- NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
- NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
- NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
- NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
- NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
- NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
- NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
- NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
- NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
- NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
- NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
- NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
- NewCRC[20]=C[12]^C[28]^D[3];
- NewCRC[21]=C[13]^C[29]^D[2];
- NewCRC[22]=C[14]^C[24]^D[7];
- NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
- NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
- NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
- NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
- NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
- NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
- NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
- NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
- NewCRC[31]=C[23]^C[29]^D[2];
- NextCRC=NewCRC;
- end
- endfunction
-
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- CRC_reg <=32'hffffffff;
- else if (CRC_init)
- CRC_reg <=32'hffffffff;
- else if (CRC_en)
- CRC_reg <=NextCRC(CRC_data,CRC_reg);
-
-assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
-
-endmodule
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