1 files changed, 23 insertions, 0 deletions
diff --git a/usrp2/fpga/eth/bench/verilog/test.scr b/usrp2/fpga/eth/bench/verilog/test.scr
new file mode 100644
index 000000000..2ad127d31
--- /dev/null
+++ b/usrp2/fpga/eth/bench/verilog/test.scr
@@ -0,0 +1,23 @@
+// This tests just runs trough a couple of different packet lengths
+
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
+// Set speed to 1000 Mbps
+01 00 22 00 04
+
+// Setup Tx and Rx MAC addresses and type field to "IP"
+// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
+10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
+
+// Transmit a 320-byte frame 1 time - and expect it to be received again!
+20 01 40 00 01
+
+// Transmit a 80-byte frame 1 time - and expect it to be received again!
+20 00 50 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
+// Halt
+FF