1 files changed, 14 insertions, 0 deletions
diff --git a/usrp2/fpga/eth/bench/verilog/miim_model.v b/usrp2/fpga/eth/bench/verilog/miim_model.v
new file mode 100644
index 000000000..936d99a80
--- /dev/null
+++ b/usrp2/fpga/eth/bench/verilog/miim_model.v
@@ -0,0 +1,14 @@
+
+// Skeleton PHY interface simulator
+
+module miim_model(input mdc_i, 
+		  inout mdio, 
+		  input phy_resetn_i, 
+		  input phy_clk_i, 
+		  output phy_intn_o,
+		  output [2:0] speed_o);
+
+   assign 		       phy_intn_o = 1;    // No interrupts
+   assign 		       speed_o = 3'b100;  // 1G mode
+   
+endmodule // miim_model