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path: root/usrp2/fpga/control_lib/WB_SIM.sav
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-rw-r--r--usrp2/fpga/control_lib/WB_SIM.sav47
1 files changed, 47 insertions, 0 deletions
diff --git a/usrp2/fpga/control_lib/WB_SIM.sav b/usrp2/fpga/control_lib/WB_SIM.sav
new file mode 100644
index 000000000..467cd35ef
--- /dev/null
+++ b/usrp2/fpga/control_lib/WB_SIM.sav
@@ -0,0 +1,47 @@
+[size] 1400 971
+[pos] -1 -1
+*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+wb_sim.wb_rst
+wb_sim.wb_clk
+@23
+wb_sim.rom_data[47:0]
+@22
+wb_sim.rom_addr[15:0]
+@28
+wb_sim.start
+wb_sim.wb_ack
+@22
+wb_sim.wb_adr[15:0]
+@28
+wb_sim.wb_cyc
+@22
+wb_sim.wb_dat[31:0]
+wb_sim.wb_sel[3:0]
+@28
+wb_sim.wb_stb
+wb_sim.wb_we
+@22
+wb_sim.port_output[31:0]
+@28
+wb_sim.system_control.POR
+wb_sim.system_control.aux_clk
+wb_sim.system_control.clk_fpga
+@29
+wb_sim.system_control.done
+@28
+wb_sim.system_control.dsp_clk
+wb_sim.system_control.fin_del1
+wb_sim.system_control.fin_del2
+wb_sim.system_control.fin_del3
+wb_sim.system_control.fin_ret_aux
+@29
+wb_sim.system_control.fin_ret_fpga
+@28
+wb_sim.system_control.finished
+wb_sim.system_control.reset_out
+wb_sim.system_control.start
+wb_sim.system_control.started
+wb_sim.system_control.wb_clk_o
+wb_sim.system_control.wb_rst_o
+wb_sim.system_control.wb_rst_o_alt