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-rw-r--r--usrp/host/lib/db_wbxng.cc22
-rw-r--r--usrp/host/lib/db_wbxng_adf4350.cc28
-rw-r--r--usrp/host/lib/db_wbxng_adf4350_regs.cc14
3 files changed, 43 insertions, 21 deletions
diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc
index 1c7b23265..970d8efd6 100644
--- a/usrp/host/lib/db_wbxng.cc
+++ b/usrp/host/lib/db_wbxng.cc
@@ -203,13 +203,19 @@ wbxng_base::set_freq(double freq)
actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
*/
- freq_t int_freq = (freq_t) (freq/1000);
+ freq_t int_freq = freq_t(freq);
bool ok = d_common->_set_freq(int_freq);
- double freq_result = (double) d_common->_get_freq()*1000;
+ double freq_result = (double) d_common->_get_freq();
struct freq_result_t args = {ok, freq_result};
+ /* Wait before reading Lock Detect*/
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 10000000;
+ nanosleep(&t, NULL);
+
fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
- int_freq*1000, freq_result, _lock_detect());
+ int_freq, freq_result, _lock_detect());
// Offsetting the LO helps get the Tx carrier leakage out of the way.
// This also ensures that on Rx, we're not getting hosed by the
@@ -291,8 +297,8 @@ wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
d_common = new adf4350(_usrp, d_which, d_spi_enable);
// power up the transmit side, but don't enable the mixer
- usrp()->_write_oe(d_which,(PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
- usrp()->write_io(d_which, (power_on()|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which,(PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
//set_lo_offset(4e6);
//set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
@@ -314,7 +320,7 @@ wbxng_base_tx::shutdown()
// do whatever there is to do to shutdown
// Power down and leave the T/R switch in the R position
- usrp()->write_io(d_which, (power_off()|RX_TXN), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_off()|RX_TXN), (PLL_PDBRF|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
/*
// Power down VCO/PLL
@@ -354,9 +360,9 @@ wbxng_base_tx::set_enable(bool on)
*/
int v;
- int mask = RX_TXN | ENABLE_5 | ENABLE_33;
+ int mask = PLL_PDBRF | PLL_PDBRF | RX_TXN | ENABLE_5 | ENABLE_33;
if(on) {
- v = PLL_CE | ENABLE_5 | ENABLE_33;
+ v = PLL_PDBRF | PLL_CE | ENABLE_5 | ENABLE_33;
}
else {
v = RX_TXN;
diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index 6e74bf0c1..1facfd882 100644
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -13,11 +13,12 @@
//#include "io.h"
//#include "spi.h"
-#define INPUT_REF_FREQ FREQ_C(32e6)
+#define INPUT_REF_FREQ FREQ_C(64e6)
#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
+//#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
+#define FREQ_C(freq) uint64_t(freq)
#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
-#define MIN_INT_DIV uint16_t(300) /* minimum int divider, prescaler 4/5 only */
+#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
#define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
@@ -41,7 +42,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
/* Outputs */
d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
- d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
/* Initialize the pin levels. */
_enable(true);
@@ -104,7 +105,14 @@ adf4350::_write(uint8_t addr, uint32_t data){
s[3] = (char)(data & 0xff);
std::string str(s, 4);
+ timespec t;
+ t.tv_sec = 0;
+ t.tv_nsec = 5e6;
+
+ nanosleep(&t, NULL);
d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
+ nanosleep(&t, NULL);
+
fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
/* pulse latch */
//d_usrp->write_io(d_which, 1, LE_PIN);
@@ -122,7 +130,8 @@ adf4350::_set_freq(freq_t freq){
d_regs->d_divider_select++; //double the divider
}
/* Ramp up the R divider until the N divider is at least the minimum. */
- d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+ //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+ d_regs->d_10_bit_r_counter = 2;
uint64_t n_mod;
do{
d_regs->d_10_bit_r_counter++;
@@ -141,7 +150,14 @@ adf4350::_set_freq(freq_t freq){
}while(d_regs->d_int < MIN_INT_DIV);
/* calculate the band select so PFD is under 125 KHz */
d_regs->d_8_bit_band_select_clock_divider_value = \
- INPUT_REF_FREQ/(FREQ_C(125e3)*d_regs->d_10_bit_r_counter) + 1;
+ INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+ fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
+ d_regs->d_8_bit_band_select_clock_divider_value,
+ INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+ );
+ d_regs->_load_register(5);
+ d_regs->_load_register(3);
+ d_regs->_load_register(1);
/* load involved registers */
d_regs->_load_register(2);
d_regs->_load_register(4);
diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc
index bf39c73ca..2c1660f56 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.cc
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc
@@ -12,11 +12,11 @@ const uint8_t adf4350_regs::s_prescaler = 0;
const uint16_t adf4350_regs::s_phase = 0;
/* reg 2 */
const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
-const uint8_t adf4350_regs::s_muxout = 3;
+const uint8_t adf4350_regs::s_muxout = 6;
const uint8_t adf4350_regs::s_reference_doubler = 0;
-const uint8_t adf4350_regs::s_rdiv2 = 1;
+const uint8_t adf4350_regs::s_rdiv2 = 0;
const uint8_t adf4350_regs::s_double_buff = 0;
-const uint8_t adf4350_regs::s_charge_pump_setting = 7;
+const uint8_t adf4350_regs::s_charge_pump_setting = 5;
const uint8_t adf4350_regs::s_ldf = 0;
const uint8_t adf4350_regs::s_ldp = 0;
const uint8_t adf4350_regs::s_pd_polarity = 1;
@@ -31,11 +31,11 @@ const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
const uint8_t adf4350_regs::s_feedback_select = 1;
const uint8_t adf4350_regs::s_vco_power_down = 0;
const uint8_t adf4350_regs::s_mtld = 0;
-const uint8_t adf4350_regs::s_aux_output_select = 1;
+const uint8_t adf4350_regs::s_aux_output_select = 0;
const uint8_t adf4350_regs::s_aux_output_enable = 1;
-const uint8_t adf4350_regs::s_aux_output_power = 1;
-const uint8_t adf4350_regs::s_rf_output_enable = 0;
-const uint8_t adf4350_regs::s_output_power = 0;
+const uint8_t adf4350_regs::s_aux_output_power = 3;
+const uint8_t adf4350_regs::s_rf_output_enable = 1;
+const uint8_t adf4350_regs::s_output_power = 3;
/* reg 5 */
const uint8_t adf4350_regs::s_ld_pin_mode = 1;
generated by cgit (git 2.34.1) at 2025-01-09 20:04:48 +0000