4 files changed, 2 insertions, 2 deletions
diff --git a/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf b/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
index 340a68346..71c301333 100755
--- a/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
+++ b/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
diff --git a/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf b/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
index 340a68346..71c301333 100755
--- a/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
+++ b/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
diff --git a/usrp/fpga/sdr_lib/cordic.v b/usrp/fpga/sdr_lib/cordic.v
index fee241f62..ea4119426 100755
--- a/usrp/fpga/sdr_lib/cordic.v
+++ b/usrp/fpga/sdr_lib/cordic.v
@@ -66,7 +66,7 @@ module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
        begin
 	  x0   <= #1 0; y0   <= #1 0;  z0   <= #1 0;
        end
-     else// if(enable)
+     else if(enable)
        begin
 	  z0 <= #1 zi[zwidth-2:0];
 	  case (zi[zwidth-1:zwidth-2])
diff --git a/usrp/fpga/sdr_lib/cordic_stage.v b/usrp/fpga/sdr_lib/cordic_stage.v
index 0106da5cb..d44998b0d 100755
--- a/usrp/fpga/sdr_lib/cordic_stage.v
+++ b/usrp/fpga/sdr_lib/cordic_stage.v
@@ -45,7 +45,7 @@ module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
 	  yo <= #1 0;
 	  zo <= #1 0;
        end
-     else //if(enable)
+     else if(enable)
        begin
 	  xo <= #1 z_is_pos ?   
 		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :