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-rw-r--r--usrp/fpga/tb/cbus_tb.v71
-rw-r--r--usrp/fpga/tb/cordic_tb.v61
-rw-r--r--usrp/fpga/tb/decim_tb.v108
-rwxr-xr-xusrp/fpga/tb/fullchip_tb.v174
-rwxr-xr-xusrp/fpga/tb/interp_tb.v108
-rw-r--r--usrp/fpga/tb/justinterp_tb.v73
-rwxr-xr-xusrp/fpga/tb/makesine.pl14
-rwxr-xr-xusrp/fpga/tb/run_cordic4
-rwxr-xr-xusrp/fpga/tb/run_fullchip4
-rwxr-xr-xusrp/fpga/tb/usrp_tasks.v145
10 files changed, 762 insertions, 0 deletions
diff --git a/usrp/fpga/tb/cbus_tb.v b/usrp/fpga/tb/cbus_tb.v
new file mode 100644
index 000000000..53cc1272b
--- /dev/null
+++ b/usrp/fpga/tb/cbus_tb.v
@@ -0,0 +1,71 @@
+module cbus_tb;
+
+`define ch1in_freq 0
+`define ch2in_freq 1
+`define ch3in_freq 2
+`define ch4in_freq 3
+`define ch1out_freq 4
+`define ch2out_freq 5
+`define ch3out_freq 6
+`define ch4out_freq 7
+`define rates 8
+`define misc 9
+
+ task send_config_word;
+ input [7:0] addr;
+ input [31:0] data;
+ integer i;
+
+ begin
+ #10 serenable = 1;
+ for(i=7;i>=0;i=i-1)
+ begin
+ #10 serdata = addr[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ for(i=31;i>=0;i=i-1)
+ begin
+ #10 serdata = data[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ #10 serenable = 0;
+ // #10 serclk = 1;
+ // #10 serclk = 0;
+ end
+ endtask // send_config_word
+
+ initial $dumpfile("cbus_tb.vcd");
+ initial $dumpvars(0,cbus_tb);
+
+ initial reset = 1;
+ initial #500 reset = 0;
+
+ reg serclk, serdata, serenable, reset;
+ wire SDO;
+
+ control_bus control_bus
+ ( .serial_clock(serclk),
+ .serial_data_in(serdata),
+ .enable(serenable),
+ .reset(reset),
+ .serial_data_out(SDO) );
+
+
+ initial
+ begin
+ #1000 send_config_word(8'd1,32'hDEAD_BEEF);
+ #1000 send_config_word(8'd3,32'hDDEE_FF01);
+ #1000 send_config_word(8'd19,32'hFFFF_FFFF);
+ #1000 send_config_word(8'd23,32'h1234_FEDC);
+ #1000 send_config_word(8'h80,32'h0);
+ #1000 send_config_word(8'h81,32'h0);
+ #1000 send_config_word(8'h82,32'h0);
+ #1000 reset = 1;
+ #1 $finish;
+ end
+
+endmodule // cbus_tb
diff --git a/usrp/fpga/tb/cordic_tb.v b/usrp/fpga/tb/cordic_tb.v
new file mode 100644
index 000000000..ed85b37b1
--- /dev/null
+++ b/usrp/fpga/tb/cordic_tb.v
@@ -0,0 +1,61 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+module cordic_tb();
+
+ cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );
+
+ reg reset;
+ reg clk;
+ reg enable;
+ reg [15:0] xi, yi, zi;
+
+ initial reset = 1'b1;
+ initial #1000 reset = 1'b0;
+
+ initial clk = 1'b0;
+ always #50 clk <= ~clk;
+
+ initial enable = 1'b1;
+
+ initial zi = 16'b0;
+
+ always @(posedge clk)
+ zi <= #1 zi + 16'd0;
+
+ wire [15:0] xo,yo,zo;
+
+ initial $dumpfile("cordic.vcd");
+ initial $dumpvars(0,cordic_tb);
+ initial
+ begin
+`include "sine.txt"
+ end
+
+ wire [15:0] xiu = {~xi[15],xi[14:0]};
+ wire [15:0] yiu = {~yi[15],yi[14:0]};
+ wire [15:0] xou = {~xo[15],xo[14:0]};
+ wire [15:0] you = {~yo[15],yo[14:0]};
+ initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);
+
+endmodule // cordic_tb
diff --git a/usrp/fpga/tb/decim_tb.v b/usrp/fpga/tb/decim_tb.v
new file mode 100644
index 000000000..ecf20cf4a
--- /dev/null
+++ b/usrp/fpga/tb/decim_tb.v
@@ -0,0 +1,108 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+module decim_tb();
+
+`include "usrp_tasks.v"
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ reg tb_oe;
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("decim_tb.vcd");
+ $dumpvars(0, fc_tb);
+end
+
+initial #100000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+reg [7:0] counter_decim;
+wire [7:0] decim_rate;
+assign decim_rate = 32;
+initial $monitor(dac1_data);
+
+ always @(posedge clk_120mhz)
+ begin
+ if(reset | ~enable_tx)
+ counter_decim <= #1 0;
+ else if(counter_decim == 0)
+ counter_decim <= #1 decim_rate - 8'b1;
+ else
+ counter_decim <= #1 counter_decim - 8'b1;
+ end
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #48 clk_120mhz = ~clk_120mhz;
+always #120 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+
+initial enable_tx = 1'b1;
+
+ wire [31:0] decim_out, q_decim_out;
+ wire [31:0] decim_out;
+ wire [31:0] phase;
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+endmodule
diff --git a/usrp/fpga/tb/fullchip_tb.v b/usrp/fpga/tb/fullchip_tb.v
new file mode 100755
index 000000000..c446ff0e1
--- /dev/null
+++ b/usrp/fpga/tb/fullchip_tb.v
@@ -0,0 +1,174 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+`timescale 1ns/1ns
+
+module fullchip_tb();
+
+`include "usrp_tasks.v"
+
+fullchip fullchip
+ (
+ .clk_120mhz(clk_120mhz),
+ .reset(reset),
+ .enable_rx(enable_rx),
+ .enable_tx(enable_tx),
+ .SLD(serload),
+ .SEN(serenable),
+ .clear_status(),
+ .SDI(serdata),
+ .SCLK(serclk),
+
+ .adc1_data(adc1_data),
+ .adc2_data(adc2_data),
+ .adc3_data(adc1_data),
+ .adc4_data(adc2_data),
+
+ .dac1_data(dac1_data),
+ .dac2_data(dac2_data),
+ .dac3_data(),.dac4_data(),
+
+ .adclk0(adclk),.adclk1(),
+
+ .adc_oeb(),.adc_otr(4'b0),
+
+ .clk_out(clk_out),
+
+ .misc_pins(),
+
+ // USB interface
+ .usbclk(usbclk),.usbctl(usbctl),
+ .usbrdy(usbrdy),.usbdata(usbdata)
+ );
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ wire have_packet_rdy = usbrdy[1];
+
+ reg tb_oe;
+ initial tb_oe=1'b1;
+
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("fullchip_tb.vcd");
+ $dumpvars(0, fullchip_tb);
+end
+
+//initial #1000000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+//initial $monitor(dac1_data);
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #24 clk_120mhz = ~clk_120mhz;
+always #60 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+/////////////////////////////////////////////////
+// Run AD input
+
+always @(posedge adclk) adc1_data <= #1 12'd1234;
+always @(posedge adclk) adc2_data <= #1 12'd1234;
+
+/////////////////////////////////////////////////
+// USB interface
+
+ initial
+ begin
+ initialize_usb;
+ #30000 @(posedge usbclk);
+ burst_usb_write(257);
+
+ #30000 burst_usb_read(256);
+ #10000 $finish;
+
+// repeat(30)
+// begin
+// write_from_usb;
+// read_from_usb;
+// end
+end
+
+/////////////////////////////////////////////////
+// TX and RX enable
+
+initial enable_tx = 1'b0;
+initial #40000 enable_tx = 1'b1;
+initial enable_rx = 1'b0;
+initial #40000 enable_rx = 1'b1;
+
+//////////////////////////////////////////////////
+// Set up control bus
+
+initial
+begin
+ #1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock
+ send_config_word(`ch2in_freq,32'h0);
+ send_config_word(`ch3in_freq,32'h0);
+ send_config_word(`ch4in_freq,32'h0);
+ send_config_word(`ch1out_freq,32'h01234567);
+ send_config_word(`ch2out_freq,32'h0);
+ send_config_word(`ch3out_freq,32'h0);
+ send_config_word(`ch4out_freq,32'h0);
+ send_config_word(`misc,32'h0);
+ send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07});
+ // adc, ext, interp, decim
+end
+
+/////////////////////////////////////////////////////////
+
+endmodule
+
diff --git a/usrp/fpga/tb/interp_tb.v b/usrp/fpga/tb/interp_tb.v
new file mode 100755
index 000000000..8a8e89ff9
--- /dev/null
+++ b/usrp/fpga/tb/interp_tb.v
@@ -0,0 +1,108 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+module interp_tb();
+
+`include "usrp_tasks.v"
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ reg tb_oe;
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("interp_tb.vcd");
+ $dumpvars(0, fc_tb);
+end
+
+initial #100000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+reg [7:0] counter_interp;
+wire [7:0] interp_rate;
+assign interp_rate = 32;
+initial $monitor(dac1_data);
+
+ always @(posedge clk_120mhz)
+ begin
+ if(reset | ~enable_tx)
+ counter_interp <= #1 0;
+ else if(counter_interp == 0)
+ counter_interp <= #1 interp_rate - 8'b1;
+ else
+ counter_interp <= #1 counter_interp - 8'b1;
+ end
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #48 clk_120mhz = ~clk_120mhz;
+always #120 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+
+initial enable_tx = 1'b1;
+
+ wire [31:0] interp_out, q_interp_out;
+ wire [31:0] decim_out;
+ wire [31:0] phase;
+
+ cic_interp #(.bitwidth(32),.stages(4))
+ interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out));
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+endmodule
diff --git a/usrp/fpga/tb/justinterp_tb.v b/usrp/fpga/tb/justinterp_tb.v
new file mode 100644
index 000000000..ffbd0f178
--- /dev/null
+++ b/usrp/fpga/tb/justinterp_tb.v
@@ -0,0 +1,73 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module cic_decim_tb;
+
+cic_decim #(.bitwidth(16),.stages(4))
+ decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
+
+ reg clock;
+ reg reset;
+ reg enable;
+ wire strobe;
+ reg [15:0] signal_in;
+ wire [15:0] signal_out;
+
+ assign strobe_in = 1'b1;
+ reg strobe_out;
+
+ always @(posedge clock)
+ while(1)
+ begin
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ strobe_out <= 1'b1;
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ strobe_out <= 1'b0;
+ end
+
+ initial clock = 0;
+ always #50 clock = ~clock;
+
+ initial reset = 1;
+ initial #1000 reset = 0;
+
+ initial enable = 0;
+ initial #2000 enable = 1;
+
+ initial signal_in = 16'h1;
+ initial #500000 signal_in = 16'h7fff;
+ initial #1000000 signal_in = 16'h8000;
+ initial #1500000 signal_in = 16'hffff;
+
+
+ initial $dumpfile("decim.vcd");
+ initial $dumpvars(0,cic_decim_tb);
+
+ initial #10000000 $finish;
+
+endmodule // cic_decim_tb
diff --git a/usrp/fpga/tb/makesine.pl b/usrp/fpga/tb/makesine.pl
new file mode 100755
index 000000000..9aebd6947
--- /dev/null
+++ b/usrp/fpga/tb/makesine.pl
@@ -0,0 +1,14 @@
+#!/usr/bin/perl
+
+$angle = 0;
+$angle_inc = 2*3.14159/87.2;
+$amp = 1;
+$amp_rate = 1.0035;
+for($i=0;$i<3500;$i++)
+ {
+ printf("@(posedge clk);xi<= #1 16'h%x;yi<= #1 16'h%x;\n",65535&int($amp*cos($angle)),65535&int($amp*sin($angle)));
+ $angle += $angle_inc;
+ $amp *= $amp_rate;
+ }
+
+printf("\$finish;\n");
diff --git a/usrp/fpga/tb/run_cordic b/usrp/fpga/tb/run_cordic
new file mode 100755
index 000000000..68144fc83
--- /dev/null
+++ b/usrp/fpga/tb/run_cordic
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y ../sdr_lib -o cordic_tb cordic_tb.v
+
diff --git a/usrp/fpga/tb/run_fullchip b/usrp/fpga/tb/run_fullchip
new file mode 100755
index 000000000..eb81d7ff7
--- /dev/null
+++ b/usrp/fpga/tb/run_fullchip
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y ../toplevel/fullchip -y ../sdr_lib -y ../models -y . -o fullchip_tb fullchip_tb.v
+
diff --git a/usrp/fpga/tb/usrp_tasks.v b/usrp/fpga/tb/usrp_tasks.v
new file mode 100755
index 000000000..00f82b9e1
--- /dev/null
+++ b/usrp/fpga/tb/usrp_tasks.v
@@ -0,0 +1,145 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Tasks
+
+/////////////////////////////////////////////////
+// USB interface
+
+task initialize_usb;
+begin
+ OE = 0;WE = 0;RD = 0;
+ usbdatareg <= 16'h0;
+end
+endtask
+
+task write_from_usb;
+begin
+ tb_oe <= 1'b1;
+ @(posedge usbclk);
+ usbdatareg <= #1 $random % 65536;
+ WE <= #1 1'b1;
+ @(posedge usbclk)
+ WE <= #1 1'b0;
+ tb_oe <= #1 1'b0;
+end
+endtask
+
+task burst_usb_write;
+ input [31:0] repeat_count;
+
+ begin
+ tb_oe <= 1'b1;
+ repeat(repeat_count)
+ begin
+ @(posedge usbclk)
+ usbdatareg <= #1 usbdatareg + 1; //$random % 65536;
+ WE <= #1 1'b1;
+ end
+ @(posedge usbclk)
+ WE <= #1 1'b0;
+ tb_oe <= 1'b0;
+ end
+endtask // burst_usb_write
+
+
+task read_from_usb;
+begin
+ @(posedge usbclk);
+ RD <= #1 1'b1;
+ @(posedge usbclk);
+ RD <= #1 1'b0;
+ OE <= #1 1'b1;
+ @(posedge usbclk);
+ OE <= #1 1'b0;
+end
+endtask
+
+task burst_usb_read;
+ input [31:0] repeat_count;
+ begin
+ while (~have_packet_rdy) begin
+ @(posedge usbclk);
+ end
+
+ @(posedge usbclk)
+ RD <= #1 1'b1;
+ repeat(repeat_count)
+ begin
+ @(posedge usbclk)
+ OE <= #1 1'b1;
+ end
+ RD <= #1 1'b0;
+ @(posedge usbclk);
+ OE <= #1 1'b0;
+ end
+endtask // burst_usb_read
+
+/////////////////////////////////////////////////
+// TX and RX enable
+
+//////////////////////////////////////////////////
+// Set up control bus
+
+`define ch1in_freq 0
+`define ch2in_freq 1
+`define ch3in_freq 2
+`define ch4in_freq 3
+`define ch1out_freq 4
+`define ch2out_freq 5
+`define ch3out_freq 6
+`define ch4out_freq 7
+`define rates 8
+`define misc 9
+
+ task send_config_word;
+ input [7:0] addr;
+ input [31:0] data;
+ integer i;
+
+ begin
+ #10 serenable = 1;
+ for(i=7;i>=0;i=i-1)
+ begin
+ #10 serdata = addr[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ for(i=31;i>=0;i=i-1)
+ begin
+ #10 serdata = data[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ #10 serenable = 0;
+ // #10 serload = 0;
+ // #10 serload = 1;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ //#10 serload = 0;
+ end
+ endtask // send_config_word
+
+
+/////////////////////////////////////////////////////////
+
generated by cgit (git 2.34.1) at 2024-12-21 05:20:59 +0000