summaryrefslogtreecommitdiff
path: root/usrp/fpga/models
diff options
context:
space:
mode:
Diffstat (limited to 'usrp/fpga/models')
-rw-r--r--usrp/fpga/models/bustri.v17
-rw-r--r--usrp/fpga/models/fifo.v81
-rw-r--r--usrp/fpga/models/fifo_1c_1k.v81
-rw-r--r--usrp/fpga/models/fifo_1c_2k.v81
-rw-r--r--usrp/fpga/models/fifo_1c_4k.v76
-rw-r--r--usrp/fpga/models/fifo_1k.v24
-rw-r--r--usrp/fpga/models/fifo_2k.v24
-rw-r--r--usrp/fpga/models/fifo_4k.v24
-rw-r--r--usrp/fpga/models/pll.v33
-rw-r--r--usrp/fpga/models/ssram.v38
10 files changed, 479 insertions, 0 deletions
diff --git a/usrp/fpga/models/bustri.v b/usrp/fpga/models/bustri.v
new file mode 100644
index 000000000..6e5a0f74c
--- /dev/null
+++ b/usrp/fpga/models/bustri.v
@@ -0,0 +1,17 @@
+
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+ enabledt,
+ tridata);
+
+ input [15:0] data;
+ input enabledt;
+ inout [15:0] tridata;
+
+ assign tridata = enabledt ? data :16'bz;
+
+endmodule // bustri
+
+
diff --git a/usrp/fpga/models/fifo.v b/usrp/fpga/models/fifo.v
new file mode 100644
index 000000000..a04e7da6c
--- /dev/null
+++ b/usrp/fpga/models/fifo.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 16;
+ parameter depth = 1024;
+ parameter addr_bits = 10;
+
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [width-1:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [width-1:0] q;
+ output rdfull;
+ output rdempty;
+ output reg [addr_bits-1:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output reg [addr_bits-1:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [addr_bits-1:0] rdptr;
+ reg [addr_bits-1:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_1k
+
diff --git a/usrp/fpga/models/fifo_1c_1k.v b/usrp/fpga/models/fifo_1c_1k.v
new file mode 100644
index 000000000..d11040b54
--- /dev/null
+++ b/usrp/fpga/models/fifo_1c_1k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 1024;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [9:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [9:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [9:0] rdusedw;
+ reg [9:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_1k
diff --git a/usrp/fpga/models/fifo_1c_2k.v b/usrp/fpga/models/fifo_1c_2k.v
new file mode 100644
index 000000000..5c3acfef5
--- /dev/null
+++ b/usrp/fpga/models/fifo_1c_2k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 2048;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [10:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [10:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [10:0] rdusedw;
+ reg [10:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_2k
diff --git a/usrp/fpga/models/fifo_1c_4k.v b/usrp/fpga/models/fifo_1c_4k.v
new file mode 100644
index 000000000..3e5ddd052
--- /dev/null
+++ b/usrp/fpga/models/fifo_1c_4k.v
@@ -0,0 +1,76 @@
+// Model of FIFO in Altera
+
+module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 4096;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [7:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [7:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [7:0] rdusedw;
+ reg [7:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+
+endmodule // fifo_1c_4k
diff --git a/usrp/fpga/models/fifo_1k.v b/usrp/fpga/models/fifo_1k.v
new file mode 100644
index 000000000..acfa4d176
--- /dev/null
+++ b/usrp/fpga/models/fifo_1k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_1k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [9:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [9:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/usrp/fpga/models/fifo_2k.v b/usrp/fpga/models/fifo_2k.v
new file mode 100644
index 000000000..50cd7811d
--- /dev/null
+++ b/usrp/fpga/models/fifo_2k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_2k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [10:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [10:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/usrp/fpga/models/fifo_4k.v b/usrp/fpga/models/fifo_4k.v
new file mode 100644
index 000000000..1fa4ba0a7
--- /dev/null
+++ b/usrp/fpga/models/fifo_4k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_4k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [11:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [11:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/usrp/fpga/models/pll.v b/usrp/fpga/models/pll.v
new file mode 100644
index 000000000..d87964844
--- /dev/null
+++ b/usrp/fpga/models/pll.v
@@ -0,0 +1,33 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Very simple model for the PLL in the RX buffer
+
+module pll (inclk0,c0);
+
+ input inclk0;
+ output c0;
+
+ assign c0 = #9 inclk0;
+
+endmodule // pll
+
+
diff --git a/usrp/fpga/models/ssram.v b/usrp/fpga/models/ssram.v
new file mode 100644
index 000000000..fd7339970
--- /dev/null
+++ b/usrp/fpga/models/ssram.v
@@ -0,0 +1,38 @@
+
+// Model of Pipelined [ZBT] Synchronous SRAM
+
+module ssram(clock,addr,data,wen,ce);
+ parameter addrbits = 19;
+ parameter depth = 524288;
+
+ input clock;
+ input [addrbits-1:0] addr;
+ inout [35:0] data;
+ input wen;
+ input ce;
+
+ reg [35:0] ram [0:depth-1];
+
+ reg read_d1,read_d2;
+ reg write_d1,write_d2;
+ reg [addrbits-1:0] addr_d1,addr_d2;
+
+ always @(posedge clock)
+ begin
+ read_d1 <= #1 ce & ~wen;
+ write_d1 <= #1 ce & wen;
+ addr_d1 <= #1 addr;
+ read_d2 <= #1 read_d1;
+ write_d2 <= #1 write_d1;
+ addr_d2 <= #1 addr_d1;
+ if(write_d2)
+ ram[addr_d2] = data;
+ end // always @ (posedge clock)
+
+ data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
+
+ always @(posedge clock)
+ if(~ce & (write_d2 | write_d1 | wen))
+ $display("$time ERROR: RAM CE not asserted during write cycle");
+
+endmodule // ssram
generated by cgit (git 2.34.1) at 2024-12-21 04:03:33 +0000