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-rw-r--r--usrp/fpga/models/fifo_4k_18.v26
1 files changed, 0 insertions, 26 deletions
diff --git a/usrp/fpga/models/fifo_4k_18.v b/usrp/fpga/models/fifo_4k_18.v
deleted file mode 100644
index 3efbf74f0..000000000
--- a/usrp/fpga/models/fifo_4k_18.v
+++ /dev/null
@@ -1,26 +0,0 @@
-
-
-module fifo_4k_18
- (input [17:0] data,
- input wrreq,
- input wrclk,
- output wrfull,
- output wrempty,
- output [11:0] wrusedw,
-
- output [17:0] q,
- input rdreq,
- input rdclk,
- output rdfull,
- output rdempty,
- output [11:0] rdusedw,
-
- input aclr );
-
-fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k
- ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
- rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
-
-endmodule // fifo_4k_18
-
-