diff options
Diffstat (limited to 'usrp-hw/sym/generated/ep2c20-f484-PWR.src')
| -rw-r--r-- | usrp-hw/sym/generated/ep2c20-f484-PWR.src | 190 |
1 files changed, 0 insertions, 190 deletions
diff --git a/usrp-hw/sym/generated/ep2c20-f484-PWR.src b/usrp-hw/sym/generated/ep2c20-f484-PWR.src deleted file mode 100644 index 5c1b77485..000000000 --- a/usrp-hw/sym/generated/ep2c20-f484-PWR.src +++ /dev/null @@ -1,190 +0,0 @@ -# This is the template file for creating symbols with tragesym -# every line starting with '#' is a comment line. - -[options] -# rotate_labels rotates the pintext of top and bottom pins -# wordswap swaps labels if the pin is on the right side an looks like this: -# "PB1 (CLK)" -wordswap=yes -rotate_labels=yes -sort_labels=no -generate_pinseq=yes -sym_width=2800 -pinwidthvertikal=400 -pinwidthhorizontal=400 - -[geda_attr] -# name will be printed in the top of the symbol -# if you have a device with slots, you'll have to use slot= and slotdef= -# use comment= if there are special information you want to add -version=20030525 -name=EP2C20-F484-PWR -device=EP2C20-F484 -refdes=U? -footprint=FG484 -description=EP2C20 Cyclone II FPGA -documentation=http://www.altera.com -author=mettus -numslots=0 -#slot=1 -#slotdef=1: -#slotdef=2: -#slotdef=3: -#slotdef=4: -#comment= -#comment= -#comment= - -[pins] -# tabseparated list of pin descriptions -# pinnr is the physical number of the pin -# seq is the pinseq= attribute, leave it blank if it doesn't matter -# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) -# style can be (line,dot,clk,dotclk,none). none if only want to add a net -# posit. can be (l,r,t,b) or empty for nets -# net specifies the name of the Vcc or GND name -# label represents the pinlabel. -# negation lines can be added with _Q_ -# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences -#----------------------------------------------------- -#pinnr seq type style posit. net label -#----------------------------------------------------- -U5 pwr line r GND\_PLL1 -U6 pwr line l VCCD\_PLL1 -U7 pwr line l VCCA\_PLL1 -V7 pwr line r GNDA\_PLL1 -V5 pwr line r GND\_PLL1 - -E16 pwr line r GNDA\_PLL2 -E17 pwr line r GND\_PLL2 -F16 pwr line l VCCA\_PLL2 -F17 pwr line l VCCD\_PLL2 -F18 pwr line r GND\_PLL2 - -F5 pwr line r GND\_PLL3 -E5 pwr line l VCCD\_PLL3 -F6 pwr line r GND\_PLL3 -F7 pwr line r GNDA\_PLL3 -E6 pwr line l VCCA\_PLL3 - -V18 pwr line r GND\_PLL4 -U17 pwr line l VCCD\_PLL4 -T17 pwr line r GND\_PLL4 -V16 pwr line r GNDA\_PLL4 -U16 pwr line l VCCA\_PLL4 - -K10 pwr line r GND -K11 pwr line r GND -K12 pwr line r GND -K13 pwr line r GND -L10 pwr line r GND -L11 pwr line r GND -L12 pwr line r GND -L13 pwr line r GND -M10 pwr line r GND -M11 pwr line r GND -M12 pwr line r GND -M13 pwr line r GND -N10 pwr line r GND -N11 pwr line r GND -N12 pwr line r GND -N13 pwr line r GND -A1 pwr line r GND -A22 pwr line r GND -AA2 pwr line r GND -AA21 pwr line r GND -AB1 pwr line r GND -AB22 pwr line r GND -B2 pwr line r GND -B21 pwr line r GND -C5 pwr line r GND -C8 pwr line r GND -C15 pwr line r GND -D10 pwr line r GND -D13 pwr line r GND -D18 pwr line r GND -F19 pwr line r GND -G4 pwr line r GND -G10 pwr line r GND -G13 pwr line r GND -H20 pwr line r GND -K3 pwr line r GND -K7 pwr line r GND -K16 pwr line r GND -K19 pwr line r GND -M4 pwr line r GND -N7 pwr line r GND -N16 pwr line r GND -N19 pwr line r GND -R3 pwr line r GND -T10 pwr line r GND -T13 pwr line r GND -T20 pwr line r GND -V3 pwr line r GND -V6 pwr line r GND -V17 pwr line r GND -W10 pwr line r GND -W13 pwr line r GND -W19 pwr line r GND -Y8 pwr line r GND -Y15 pwr line r GND - -J10 pwr line l VccInt -J11 pwr line l VccInt -J12 pwr line l VccInt -J13 pwr line l VccInt -K9 pwr line l VccInt -K14 pwr line l VccInt -L9 pwr line l VccInt -L14 pwr line l VccInt -M9 pwr line l VccInt -M14 pwr line l VccInt -N9 pwr line l VccInt -N14 pwr line l VccInt -P10 pwr line l VccInt -P11 pwr line l VccInt -P12 pwr line l VccInt -P13 pwr line l VccInt - -AA1 pwr line l VccIO1 -M3 pwr line l VccIO1 -P7 pwr line l VccIO1 -T4 pwr line l VccIO1 - -B1 pwr line l VccIO2 -J7 pwr line l VccIO2 -L3 pwr line l VccIO2 - -A2 pwr line l VccIO3 -C6 pwr line l VccIO3 -C11 pwr line l VccIO3 -E10 pwr line l VccIO3 -G9 pwr line l VccIO3 - -A21 pwr line l VccIO4 -C12 pwr line l VccIO4 -D17 pwr line l VccIO4 -E13 pwr line l VccIO4 -G14 pwr line l VccIO4 - -B22 pwr line l VccIO5 -G19 pwr line l VccIO5 -J16 pwr line l VccIO5 -L20 pwr line l VccIO5 - -AA22 pwr line l VccIO6 -M20 pwr line l VccIO6 -P16 pwr line l VccIO6 -T19 pwr line l VccIO6 - -AB21 pwr line l VccIO7 -T14 pwr line l VccIO7 -V13 pwr line l VccIO7 -W17 pwr line l VccIO7 -Y12 pwr line l VccIO7 - -AB2 pwr line l VccIO8 -T9 pwr line l VccIO8 -V10 pwr line l VccIO8 -W6 pwr line l VccIO8 -Y11 pwr line l VccIO8 |