1 files changed, 0 insertions, 59 deletions
diff --git a/usrp-hw/sym/generated/ep2c20-f484-CFG.src b/usrp-hw/sym/generated/ep2c20-f484-CFG.src
deleted file mode 100644
index 5d0083824..000000000
--- a/usrp-hw/sym/generated/ep2c20-f484-CFG.src
+++ /dev/null
@@ -1,59 +0,0 @@
-# This is the template file for creating symbols with tragesym
-# every line starting with '#' is a comment line.
-
-[options]
-# rotate_labels rotates the pintext of top and bottom pins
-# wordswap swaps labels if the pin is on the right side an looks like this:
-# "PB1 (CLK)"
-wordswap=yes
-rotate_labels=yes
-sort_labels=no
-generate_pinseq=yes
-sym_width=2800
-pinwidthvertikal=400
-pinwidthhorizontal=400
-
-[geda_attr]
-# name will be printed in the top of the symbol
-# if you have a device with slots, you'll have to use slot= and slotdef=
-# use comment= if there are special information you want to add
-version=20030525
-name=EP2C20-F484-CFG
-device=EP2C20-F484
-refdes=U?
-footprint=FG484
-description=EP2C20 Cyclone II FPGA
-documentation=http://www.altera.com
-author=mettus
-numslots=0
-#slot=1
-#slotdef=1:
-#slotdef=2:
-#slotdef=3:
-#slotdef=4:
-#comment=
-#comment=
-#comment=
-
-[pins]
-# tabseparated list of pin descriptions
-# pinnr is the physical number of the pin
-# seq is the pinseq= attribute, leave it blank if it doesn't matter
-# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
-# style can be (line,dot,clk,dotclk,none). none if only want to add a net
-# posit. can be (l,r,t,b) or empty for nets
-# net specifies the name of the Vcc or GND name
-# label represents the pinlabel. 
-#	negation lines can be added with _Q_ 
-#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
-#-----------------------------------------------------
-#pinnr	seq	type	style	posit.	net	label	
-#-----------------------------------------------------
-L6		in	line	l		DCLK
-K4		in	line	l		DATA0
-K1		in	line	l		_nCE_
-L4		in	line	l		_nCONFIG_
-N20		in	line	l		_nSTATUS_
-N18		in	line	l		CONF\_DONE
-N17		in	line	l		MSEL1
-M17		in	line	l		MSEL0