summaryrefslogtreecommitdiff
path: root/gr-usrp2/src
diff options
context:
space:
mode:
Diffstat (limited to 'gr-usrp2/src')
-rw-r--r--gr-usrp2/src/usrp2.i3
-rw-r--r--gr-usrp2/src/usrp2_base.cc12
-rw-r--r--gr-usrp2/src/usrp2_base.h12
3 files changed, 26 insertions, 1 deletions
diff --git a/gr-usrp2/src/usrp2.i b/gr-usrp2/src/usrp2.i
index 3d6da0606..319740283 100644
--- a/gr-usrp2/src/usrp2.i
+++ b/gr-usrp2/src/usrp2.i
@@ -31,6 +31,7 @@
%}
%include <usrp2/tune_result.h>
+%include <usrp2/mimo_config.h>
%template(uint32_t_vector) std::vector<uint32_t>;
@@ -48,7 +49,9 @@ public:
std::string interface_name() const;
%rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
bool fpga_master_clock_freq(long *freq);
+ bool config_mimo(int flags);
bool sync_to_pps();
+ bool sync_every_pps(bool enable);
std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
};
diff --git a/gr-usrp2/src/usrp2_base.cc b/gr-usrp2/src/usrp2_base.cc
index 34492dc47..bb9959725 100644
--- a/gr-usrp2/src/usrp2_base.cc
+++ b/gr-usrp2/src/usrp2_base.cc
@@ -68,11 +68,23 @@ usrp2_base::fpga_master_clock_freq(long *freq) const
}
bool
+usrp2_base::config_mimo(int flags)
+{
+ return d_u2->config_mimo(flags);
+}
+
+bool
usrp2_base::sync_to_pps()
{
return d_u2->sync_to_pps();
}
+bool
+usrp2_base::sync_every_pps(bool enable)
+{
+ return d_u2->sync_every_pps(enable);
+}
+
std::vector<uint32_t>
usrp2_base::peek32(uint32_t addr, uint32_t words)
{
diff --git a/gr-usrp2/src/usrp2_base.h b/gr-usrp2/src/usrp2_base.h
index bfd1dce09..67a62ba10 100644
--- a/gr-usrp2/src/usrp2_base.h
+++ b/gr-usrp2/src/usrp2_base.h
@@ -1,6 +1,6 @@
/* -*- c++ -*- */
/*
- * Copyright 2008 Free Software Foundation, Inc.
+ * Copyright 2008,2009 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
@@ -64,11 +64,21 @@ public:
bool fpga_master_clock_freq(long *freq) const;
/*!
+ * \brief MIMO configuration
+ */
+ bool config_mimo(int flags);
+
+ /*!
* \brief Set master time to 0 at next PPS rising edge
*/
bool sync_to_pps();
/*!
+ * Reset master time to 0 at every PPS edge
+ */
+ bool sync_every_pps(bool enable);
+
+ /*!
* \brief Read memory from Wishbone bus as words
*/
std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);