diff options
Diffstat (limited to 'gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py')
| -rwxr-xr-x | gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py b/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py index 9b6422f7a..7337c71d7 100755 --- a/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py +++ b/gr-uhd/grc/gen_uhd_single_usrp_blocks_xml.py @@ -30,6 +30,13 @@ MAIN_TMPL = """\ io_type=uhd.io_type_t.\$type.type, num_channels=\$nchan, ) +\#if \$ref_clk() +_clk_cfg = uhd.clock_config_t() +_clk_cfg.ref_source = uhd.clock_config_t.REF_SMA +_clk_cfg.pps_source = uhd.clock_config_t.PPS_SMA +_clk_cfg.pps_polarity = uhd.clock_config_t.PPS_POS +self.\$(id).set_clock_config(_clk_cfg); +\#end if \#if \$sd_spec() self.\$(id).set_subdev_spec(\$sd_spec) \#end if @@ -104,6 +111,21 @@ self.\$(id).set_bandwidth(\$bw$(n), $n) </hide> </param> <param> + <name>Ref Clock</name> + <key>ref_clk</key> + <value></value> + <type>enum</type> + <hide>\#if \$ref_clk() then 'none' else 'part'#</hide> + <option> + <name>External</name> + <key>ext</key> + </option> + <option> + <name>Internal</name> + <key></key> + </option> + </param> + <param> <name>Subdev Spec</name> <key>sd_spec</key> <value></value> |