diff options
Diffstat (limited to 'gr-radar-mono/src/fpga/lib')
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/Makefile.am | 2 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar.v | 13 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_control.v | 15 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_rx.v | 96 |
4 files changed, 62 insertions, 64 deletions
diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am index 8aefd754d..2a7d6d883 100644 --- a/gr-radar-mono/src/fpga/lib/Makefile.am +++ b/gr-radar-mono/src/fpga/lib/Makefile.am @@ -31,4 +31,4 @@ EXTRA_DIST = \ fifo32_4k.v \ cordic_nco.v -MOSTLYCLEANFILES = *~ +MOSTLYCLEANFILES = *~ *.bak diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v index 127e9cee3..d71d9397c 100644 --- a/gr-radar-mono/src/fpga/lib/radar.v +++ b/gr-radar-mono/src/fpga/lib/radar.v @@ -24,8 +24,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o, rx_adc_i_i,rx_adc_q_i, - rx_strobe_o,rx_ech_i_o,rx_ech_q_o); - + rx_strobe_o,rx_ech_i_o,rx_ech_q_o,auto_tr_o); + // System interface input clk_i; // Master clock @ 64 MHz input [6:0] saddr_i; // Configuration bus address @@ -37,7 +37,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, output tx_strobe_o; // Generate an transmitter output sample output [13:0] tx_dac_i_o; // I channel transmitter output to DAC output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC - + output auto_tr_o; // Transmit/Receive switching + // Receive subsystem input [15:0] rx_adc_i_i; // I channel input from ADC input [15:0] rx_adc_q_i; // Q channel input from ADC @@ -53,6 +54,7 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, wire rx_enable; // Receiver enable wire tx_ctrl; // Transmitter on control wire rx_ctrl; // Receiver on control + wire [15:0] pulse_num; // Count of pulses since tx_enabled // Configuration wire [15:0] ampl; // Pulse amplitude @@ -63,7 +65,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i), .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled), .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl), - .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr)); + .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num)); + assign auto_tr_o = tx_ctrl; radar_tx transmitter ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o), @@ -72,7 +75,7 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, radar_rx receiver ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled), - .rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i), + .pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i), .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) ); endmodule // radar diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v index e22da962d..864941109 100644 --- a/gr-radar-mono/src/fpga/lib/radar_control.v +++ b/gr-radar-mono/src/fpga/lib/radar_control.v @@ -21,10 +21,9 @@ `include "../lib/radar_config.vh" -module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i, - reset_o,tx_side_o,dbg_o, - tx_strobe_o,tx_ctrl_o,rx_ctrl_o, - ampl_o,fstart_o,fincr_o); +module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o, + tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o, + ampl_o,fstart_o,fincr_o,pulse_num_o); // System interface input clk_i; // Master clock @ 64 MHz @@ -42,7 +41,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i, output [15:0] ampl_o; output [31:0] fstart_o; output [31:0] fincr_o; - + output [15:0] pulse_num_o; + // Internal configuration wire lp_ena; wire md_ena; @@ -94,12 +94,14 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i, reg [3:0] state; reg [31:0] count; - + reg [15:0] pulse_num_o; + always @(posedge clk_i) if (reset_o) begin state <= `ST_ON; count <= 32'b0; + pulse_num_o <= 16'b0; end else case (state) @@ -108,6 +110,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i, begin state <= `ST_SW; count <= 32'b0; + pulse_num_o <= pulse_num_o + 16'b1; end else count <= count + 32'b1; diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v index 1ca546134..29bbadd4d 100644 --- a/gr-radar-mono/src/fpga/lib/radar_rx.v +++ b/gr-radar-mono/src/fpga/lib/radar_rx.v @@ -22,9 +22,8 @@ `include "../../../../usrp/firmware/include/fpga_regs_common.v" `include "../../../../usrp/firmware/include/fpga_regs_standard.v" -module radar_rx(clk_i,rst_i,ena_i,dbg_i, - rx_in_i_i,rx_in_q_i, - rx_i_o,rx_q_o,rx_strobe_o); +module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i, + rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o); input clk_i; input rst_i; @@ -33,11 +32,12 @@ module radar_rx(clk_i,rst_i,ena_i,dbg_i, input [15:0] rx_in_i_i; input [15:0] rx_in_q_i; + input [15:0] pulse_num_i; output [15:0] rx_i_o; output [15:0] rx_q_o; output reg rx_strobe_o; - + reg [15:0] count; always @(posedge clk_i) @@ -46,71 +46,63 @@ module radar_rx(clk_i,rst_i,ena_i,dbg_i, else count <= count + 16'b1; - wire [31:0] fifo_data = dbg_i ? {count[15:0],16'hAA55} : {rx_in_i_i,rx_in_q_i}; + wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i}; - // Need to buffer received samples as they come in at 32 bits per cycle - // but the rx_buffer.v fifo is only 16 bits wide. - // - reg fifo_read; + // Buffer incoming samples every clock wire [31:0] fifo_out; + reg fifo_ack; wire fifo_empty; + +// Use model if simulating, otherwise Altera Megacell +`ifdef SIMULATION + fifo_1clk #(32, 4096) buffer(.clock(clk_i),.sclr(rst_i), + .data(fifo_inp),.wrreq(ena_i), + .rdreq(fifo_ack),.q(fifo_out), + .empty(fifo_empty)); +`else + fifo32_4k buffer(.clock(clk_i),.sclr(rst_i), + .data(fifo_inp),.wrreq(ena_i), + .rdreq(fifo_ack),.q(fifo_out), + .empty(fifo_empty)); +`endif - fifo32_4k fifo(.clock(clk_i),.sclr(rst_i), - .data(fifo_data),.wrreq(ena_i), - .q(fifo_out),.rdreq(fifo_read), - .empty(fifo_empty) ); + // Write samples to rx_fifo every third clock + `define ST_FIFO_IDLE 3'b001 + `define ST_FIFO_STROBE 3'b010 + `define ST_FIFO_ACK 3'b100 - `define ST_RD_IDLE 4'b0001 - `define ST_RD_REQ 4'b0010 - `define ST_WR_FIFO 4'b0100 - `define ST_RD_DELAY 4'b1000 + reg [2:0] state; - reg [3:0] state; - reg [3:0] delay; - always @(posedge clk_i) - if (rst_i | ~ena_i) + if (rst_i) begin - state <= `ST_RD_IDLE; - delay <= 4'd0; + state <= `ST_FIFO_IDLE; rx_strobe_o <= 1'b0; - fifo_read <= 1'b0; + fifo_ack <= 1'b0; end else case (state) - `ST_RD_IDLE: - begin - if (!fifo_empty) - begin - fifo_read <= 1'b1; - state <= `ST_RD_REQ; - end - end - - `ST_RD_REQ: + `ST_FIFO_IDLE: + if (!fifo_empty) + begin + // Tell rx_fifo sample is ready + rx_strobe_o <= 1'b1; + state <= `ST_FIFO_STROBE; + end + `ST_FIFO_STROBE: begin - fifo_read <= 1'b0; - rx_strobe_o <= 1'b1; - state <= `ST_WR_FIFO; + rx_strobe_o <= 1'b0; + // Ack our FIFO + fifo_ack <= 1'b1; + state <= `ST_FIFO_ACK; end - - `ST_WR_FIFO: + `ST_FIFO_ACK: begin - rx_strobe_o <= 1'b0; - state <= `ST_RD_DELAY; + fifo_ack <= 1'b0; + state <= `ST_FIFO_IDLE; end - - `ST_RD_DELAY: - if (delay == 7) - begin - delay <= 0; - state <= `ST_RD_IDLE; - end - else - delay <= delay + 1'b1; - endcase // case(state) - + assign rx_i_o = fifo_out[31:16]; assign rx_q_o = fifo_out[15:0]; |