diff options
| -rw-r--r-- | usrp2/fpga/extram/extram_wb.v | 10 | ||||
| -rw-r--r-- | usrp2/fpga/extram/wb_zbt16_b.v | 63 |
2 files changed, 68 insertions, 5 deletions
diff --git a/usrp2/fpga/extram/extram_wb.v b/usrp2/fpga/extram/extram_wb.v index 8142047d7..c8428783a 100644 --- a/usrp2/fpga/extram/extram_wb.v +++ b/usrp2/fpga/extram/extram_wb.v @@ -21,7 +21,7 @@ module extram_wb wire write_acc = stb_i & cyc_i & we_i; wire acc = stb_i & cyc_i; - assign RAM_CLK = wb_clk; // 50 MHz for now, eventually should be 200 MHz + assign RAM_CLK = ~wb_clk; // 50 MHz for now, eventually should be 200 MHz assign RAM_LDn = 0; // No burst for now assign RAM_CENn = 0; // Use CE1n as our main CE @@ -63,12 +63,12 @@ module extram_wb else case(RAM_state) RAM_idle : - if(read_acc) + if(read_acc & ~ack_o) begin RAM_state <= RAM_read_1; myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0; end - else if(write_acc) + else if(write_acc & ~ack_o) begin RAM_state <= RAM_write_1; myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0; @@ -100,7 +100,7 @@ module extram_wb RAM_write_1 : begin RAM_state <= RAM_write_2; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1; + myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1; end RAM_write_2 : begin @@ -126,7 +126,7 @@ module extram_wb assign RAM_CE1n = ~RAM_EN; // Active low (RAM_state != RAM_idle); assign RAM_D[17:16] = 2'bzz; - assign RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_3)?ram_out[15:0]:ram_out[31:16]) + assign RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) : 16'bzzzz_zzzz_zzzz_zzzz; always @(posedge wb_clk) diff --git a/usrp2/fpga/extram/wb_zbt16_b.v b/usrp2/fpga/extram/wb_zbt16_b.v new file mode 100644 index 000000000..d93e21c99 --- /dev/null +++ b/usrp2/fpga/extram/wb_zbt16_b.v @@ -0,0 +1,63 @@ + +module wb_zbt16_b + (input clk, + input rst, + // Wishbone bus A, highest priority, with prefetch + input [19:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [ 1:0] wb_sel_i, + input wb_cyc_i, + input wb_stb_i, + output reg wb_ack_o, + input wb_we_i, + // Memory connection + output sram_clk, + output [18:0] sram_a, + inout [15:0] sram_d, + output sram_we, + output [ 1:0] sram_bw, + output sram_adv, + output sram_ce, + output sram_oe, + output sram_mode, + output sram_zz + ); + + assign sram_clk = ~clk; + //assign sram_oe = 1'b0; + assign sram_ce = 1'b0; + assign sram_adv = 1'b0; + assign sram_mode = 1'b0; + assign sram_zz = 1'b0; + assign sram_bw = 2'b0; + + // need to drive wb_dat_o, wb_ack_o, + // sram_a, sram_d, sram_we + wire myOE; + assign sram_d = myOE ? wb_dat_i : 16'bzzzz; + assign sram_a = wb_adr_i[19:1]; + + reg read_d1, read_d2, read_d3, write_d1, write_d2, write_d3; + wire acc = wb_cyc_i & wb_stb_i; + wire read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3; + wire write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3; + + assign sram_we = ~write_acc; + assign sram_oe = ~(read_d2 | read_d3); + assign myOE = write_d1 | write_d2; + wire latch_now = read_d2; + + always @(posedge clk) + if(latch_now) + wb_dat_o <= sram_d; + + always @(posedge clk) wb_ack_o <= read_d2 | write_d2; + always @(posedge clk) read_d1 <= read_acc; + always @(posedge clk) read_d2 <= read_d1; + always @(posedge clk) read_d3 <= read_d2; + always @(posedge clk) write_d1 <= write_acc; + always @(posedge clk) write_d2 <= write_d1; + always @(posedge clk) write_d3 <= write_d2; +endmodule // wb_zbt16_b + |