diff options
196 files changed, 8 insertions, 16879 deletions
diff --git a/config/Makefile.am b/config/Makefile.am index ba3026cd9..473f88488 100644 --- a/config/Makefile.am +++ b/config/Makefile.am @@ -54,12 +54,9 @@ m4macros = \ grc_gr_audio.m4 \ grc_gr_comedi.m4 \ grc_gr_gcell.m4 \ - grc_gr_gpio.m4 \ grc_gr_gsm_fr_vocoder.m4 \ grc_gr_noaa.m4 \ - grc_gr_radar_mono.m4 \ grc_gr_radio_astronomy.m4 \ - grc_gr_sounder.m4 \ grc_gr_trellis.m4 \ grc_gr_usrp.m4 \ grc_gr_video_sdl.m4 \ @@ -71,7 +68,6 @@ m4macros = \ gr_check_usrp.m4 \ grc_usrp.m4 \ grc_usrp2.m4 \ - grc_gr_msdd6000.m4 \ gr_doxygen.m4 \ gr_fortran.m4 \ gr_gcell.m4 \ diff --git a/config/grc_gr_gpio.m4 b/config/grc_gr_gpio.m4 deleted file mode 100644 index 26c04b95c..000000000 --- a/config/grc_gr_gpio.m4 +++ /dev/null @@ -1,38 +0,0 @@ -dnl Copyright 2007,2008,2009 Free Software Foundation, Inc. -dnl -dnl This file is part of GNU Radio -dnl -dnl GNU Radio is free software; you can redistribute it and/or modify -dnl it under the terms of the GNU General Public License as published by -dnl the Free Software Foundation; either version 3, or (at your option) -dnl any later version. -dnl -dnl GNU Radio is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY; without even the implied warranty of -dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -dnl GNU General Public License for more details. -dnl -dnl You should have received a copy of the GNU General Public License -dnl along with GNU Radio; see the file COPYING. If not, write to -dnl the Free Software Foundation, Inc., 51 Franklin Street, -dnl Boston, MA 02110-1301, USA. - -AC_DEFUN([GRC_GR_GPIO],[ - GRC_ENABLE(gr-gpio) - - dnl Don't do gr-gpio if usrp skipped - GRC_CHECK_DEPENDENCY(gr-gpio, usrp) - - AC_CONFIG_FILES([ \ - gr-gpio/Makefile \ - gr-gpio/src/Makefile \ - gr-gpio/src/fpga/Makefile \ - gr-gpio/src/fpga/include/Makefile \ - gr-gpio/src/fpga/top/Makefile \ - gr-gpio/src/fpga/lib/Makefile \ - gr-gpio/src/fpga/rbf/Makefile \ - gr-gpio/src/python/Makefile - ]) - - GRC_BUILD_CONDITIONAL(gr-gpio) -]) diff --git a/config/grc_gr_msdd6000.m4 b/config/grc_gr_msdd6000.m4 deleted file mode 100644 index 0c6fc320e..000000000 --- a/config/grc_gr_msdd6000.m4 +++ /dev/null @@ -1,38 +0,0 @@ -dnl Copyright 2001,2002,2003,2004,2005,2006,2008 Free Software Foundation, Inc. -dnl -dnl This file is part of GNU Radio -dnl -dnl GNU Radio is free software; you can redistribute it and/or modify -dnl it under the terms of the GNU General Public License as published by -dnl the Free Software Foundation; either version 3, or (at your option) -dnl any later version. -dnl -dnl GNU Radio is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY; without even the implied warranty of -dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -dnl GNU General Public License for more details. -dnl -dnl You should have received a copy of the GNU General Public License -dnl along with GNU Radio; see the file COPYING. If not, write to -dnl the Free Software Foundation, Inc., 51 Franklin Street, -dnl Boston, MA 02110-1301, USA. - -AC_DEFUN([GRC_GR_MSDD6000],[ - GRC_ENABLE([gr-msdd6000]) - - AC_CONFIG_FILES([\ - gr-msdd6000/Makefile \ - gr-msdd6000/gnuradio-msdd6000.pc \ - gr-msdd6000/src/Makefile - ]) - - dnl Don't do gr-msdd6000 if gnuradio-core skipped - GRC_CHECK_DEPENDENCY(gr-msdd6000, gnuradio-core) - - AC_CHECK_HEADERS(netinet/in.h arpa/inet.h sys/socket.h netdb.h, [], [passed=no]) - - GRC_BUILD_CONDITIONAL([gr-msdd6000],[ - dnl run_tests is created from run_tests.in. Make it executable. - dnl AC_CONFIG_COMMANDS([run_tests_msdd6000], [chmod +x gr-msdd6000/src/run_tests]) - ]) -]) diff --git a/config/grc_gr_radar_mono.m4 b/config/grc_gr_radar_mono.m4 deleted file mode 100644 index bf8e2dac4..000000000 --- a/config/grc_gr_radar_mono.m4 +++ /dev/null @@ -1,45 +0,0 @@ -dnl Copyright 2007,2008 Free Software Foundation, Inc. -dnl -dnl This file is part of GNU Radio -dnl -dnl GNU Radio is free software; you can redistribute it and/or modify -dnl it under the terms of the GNU General Public License as published by -dnl the Free Software Foundation; either version 3, or (at your option) -dnl any later version. -dnl -dnl GNU Radio is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY; without even the implied warranty of -dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -dnl GNU General Public License for more details. -dnl -dnl You should have received a copy of the GNU General Public License -dnl along with GNU Radio; see the file COPYING. If not, write to -dnl the Free Software Foundation, Inc., 51 Franklin Street, -dnl Boston, MA 02110-1301, USA. - -AC_DEFUN([GRC_GR_RADAR_MONO],[ - GRC_ENABLE(gr-radar-mono) - - dnl Don't do gr-radar-mono if usrp or gnuradio-core skipped - GRC_CHECK_DEPENDENCY(gr-radar-mono, usrp) - GRC_CHECK_DEPENDENCY(gr-radar-mono, gnuradio-core) - - AC_CONFIG_FILES([ \ - gr-radar-mono/Makefile \ - gr-radar-mono/doc/Makefile \ - gr-radar-mono/src/Makefile \ - gr-radar-mono/src/fpga/Makefile \ - gr-radar-mono/src/fpga/top/Makefile \ - gr-radar-mono/src/fpga/lib/Makefile \ - gr-radar-mono/src/fpga/models/Makefile \ - gr-radar-mono/src/fpga/tb/Makefile \ - gr-radar-mono/src/lib/Makefile \ - gr-radar-mono/src/python/Makefile \ - gr-radar-mono/src/python/run_tests - ]) - - GRC_BUILD_CONDITIONAL(gr-radar-mono,[ - dnl run_tests is created from run_tests.in. Make it executable. - AC_CONFIG_COMMANDS([run_tests_radar_mono], [chmod +x gr-radar-mono/src/python/run_tests]) - ]) -]) diff --git a/config/grc_gr_sounder.m4 b/config/grc_gr_sounder.m4 deleted file mode 100644 index 672d13ab1..000000000 --- a/config/grc_gr_sounder.m4 +++ /dev/null @@ -1,44 +0,0 @@ -dnl Copyright 2007,2008 Free Software Foundation, Inc. -dnl -dnl This file is part of GNU Radio -dnl -dnl GNU Radio is free software; you can redistribute it and/or modify -dnl it under the terms of the GNU General Public License as published by -dnl the Free Software Foundation; either version 3, or (at your option) -dnl any later version. -dnl -dnl GNU Radio is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY; without even the implied warranty of -dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -dnl GNU General Public License for more details. -dnl -dnl You should have received a copy of the GNU General Public License -dnl along with GNU Radio; see the file COPYING. If not, write to -dnl the Free Software Foundation, Inc., 51 Franklin Street, -dnl Boston, MA 02110-1301, USA. - -AC_DEFUN([GRC_GR_SOUNDER],[ - GRC_ENABLE(gr-sounder) - - dnl Don't do gr-sounder if usrp or gnuradio-core skipped - GRC_CHECK_DEPENDENCY(gr-sounder, usrp) - GRC_CHECK_DEPENDENCY(gr-sounder, gnuradio-core) - - AC_CONFIG_FILES([ \ - gr-sounder/Makefile \ - gr-sounder/doc/Makefile \ - gr-sounder/src/Makefile \ - gr-sounder/src/fpga/Makefile \ - gr-sounder/src/fpga/top/Makefile \ - gr-sounder/src/fpga/lib/Makefile \ - gr-sounder/src/fpga/tb/Makefile \ - gr-sounder/src/lib/Makefile \ - gr-sounder/src/python/Makefile \ - gr-sounder/src/python/run_tests - ]) - - GRC_BUILD_CONDITIONAL(gr-sounder,[ - dnl run_tests is created from run_tests.in. Make it executable. - AC_CONFIG_COMMANDS([run_tests_sounder], [chmod +x gr-sounder/src/python/run_tests]) - ]) -]) diff --git a/configure.ac b/configure.ac index 88589da87..1d2ca6f2a 100644 --- a/configure.ac +++ b/configure.ac @@ -358,22 +358,18 @@ GRC_USRP2 GRC_GR_USRP dnl this must come after GRC_USRP GRC_GR_USRP2 GRC_GR_GCELL dnl this must come after GRC_GCELL and GRC_GNURADIO_CORE -GRC_GR_MSDD6000 GRC_GR_AUDIO GRC_GR_ATSC GRC_GR_COMEDI GRC_GR_CVSD_VOCODER -GRC_GR_GPIO GRC_GR_GSM_FR_VOCODER GRC_GR_NOAA GRC_GR_PAGER -GRC_GR_RADAR_MONO GRC_GR_RADIO_ASTRONOMY GRC_GR_TRELLIS GRC_GR_VIDEO_SDL GRC_GR_WXGUI GRC_GR_QTGUI -GRC_GR_SOUNDER dnl this must come after GRC_USRP GRC_GR_UTILS dnl this must come after GRC_GR_WXGUI GRC_GNURADIO_EXAMPLES dnl must come after all GRC_GR_* GRC_GRC diff --git a/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.h b/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.h index 55f8412ce..385f447b7 100644 --- a/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.h +++ b/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.h @@ -48,7 +48,7 @@ class gr_frequency_modulator_fc : public gr_sync_block public: void set_sensitivity(float sens) { d_sensitivity = sens; } - float get_sensitivity() { return d_sensitivity; } + float sensitivity() const { return d_sensitivity; } int work (int noutput_items, gr_vector_const_void_star &input_items, diff --git a/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.i b/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.i index 04d9a41ba..7dfb82f1f 100644 --- a/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.i +++ b/gnuradio-core/src/lib/general/gr_frequency_modulator_fc.i @@ -30,5 +30,5 @@ class gr_frequency_modulator_fc : public gr_sync_block gr_frequency_modulator_fc (double sensitivity); public: void set_sensitivity(float sens) { d_sensitivity = sens; } - float get_sensitivity() { return d_sensitivity; } + float sensitivity() const { return d_sensitivity; } }; diff --git a/gr-gpio/.gitignore b/gr-gpio/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/Makefile.am b/gr-gpio/Makefile.am deleted file mode 100644 index d800383ef..000000000 --- a/gr-gpio/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = src diff --git a/gr-gpio/src/.gitignore b/gr-gpio/src/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/Makefile.am b/gr-gpio/src/Makefile.am deleted file mode 100644 index 5071c2273..000000000 --- a/gr-gpio/src/Makefile.am +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -SUBDIRS = fpga -if PYTHON -SUBDIRS += python -endif - diff --git a/gr-gpio/src/fpga/.gitignore b/gr-gpio/src/fpga/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/fpga/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/fpga/Makefile.am b/gr-gpio/src/fpga/Makefile.am deleted file mode 100644 index 2b6f2585e..000000000 --- a/gr-gpio/src/fpga/Makefile.am +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -SUBDIRS = include lib top rbf - diff --git a/gr-gpio/src/fpga/include/.gitignore b/gr-gpio/src/fpga/include/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/fpga/include/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/fpga/include/Makefile.am b/gr-gpio/src/fpga/include/Makefile.am deleted file mode 100644 index 3c891e5d6..000000000 --- a/gr-gpio/src/fpga/include/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - common_config_2rxhb_2tx_dig.vh \ - common_config_2rxint_2tx_dig.vh \ - common_config_bottom.vh diff --git a/gr-gpio/src/fpga/include/common_config_2rxhb_2tx_dig.vh b/gr-gpio/src/fpga/include/common_config_2rxhb_2tx_dig.vh deleted file mode 100644 index 580082c92..000000000 --- a/gr-gpio/src/fpga/include/common_config_2rxhb_2tx_dig.vh +++ /dev/null @@ -1,71 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE - `define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// If TX_DIG_ON is defined each transmit channel sends its I lsb and Q lsb to gpio pins -// The lsb bits of the analog output signal are truncated - `define TX_DIG_ON -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON - -// ------------------------------------------------------------ -// If RX_DIG_ON is defined each receive channel sends has its I lsb and Q lsb replaced by digital input from gpio pins -// So the analog signals are truncated to 15 bits - `define RX_DIG_ON diff --git a/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh b/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh deleted file mode 100644 index 01995543b..000000000 --- a/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh +++ /dev/null @@ -1,77 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE - `define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// If TX_DIG_ON is defined each transmit channel sends its I lsb and Q lsb to gpio pins -// The lsb bits of the analog output signal are truncated - `define TX_DIG_ON -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -// `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter -// This is mutually exclusive with RX_INTEG_ON -// `define RX_CIC_ON - -// ------------------------------------------------------------ -// Define RX_INTEG_ON to enable the receive single stage integrate and dump -// This is mutually exclusive with RX_CIC_ON - `define RX_INTEG_ON - -// ------------------------------------------------------------ -// If RX_DIG_ON is defined each receive channel sends has its I lsb and Q lsb replaced by digital input from gpio pins -// So the analog signals are truncated to 15 bits - `define RX_DIG_ON diff --git a/gr-gpio/src/fpga/include/common_config_bottom.vh b/gr-gpio/src/fpga/include/common_config_bottom.vh deleted file mode 100644 index 9e032642b..000000000 --- a/gr-gpio/src/fpga/include/common_config_bottom.vh +++ /dev/null @@ -1,133 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// This is the common tail for standard configuation -// ==================================================================== -// -// >>>> DO NOT EDIT BELOW HERE <<<< -// -// N.B., *all* the remainder of the code should be conditionalized -// only in terms of: -// -// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, -// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, -// RX_NCO_ON, RX_CIC_ON -// ==================================================================== - -`ifdef TX_ON - - `ifdef TX_SINGLE - `define TX_EN_0 - `ifdef TX_DIG_ON - `define TX_EN_DIG_0 - `define TX_CAP_DIG 1 - `endif - `define TX_CAP_NCHAN 3'd1 - `endif - - `ifdef TX_DUAL - `define TX_EN_0 - `define TX_EN_1 - `define TX_CAP_NCHAN 3'd2 - `ifdef TX_DIG_ON - `define TX_EN_DIG_0 - `define TX_EN_DIG_1 - `define TX_CAP_DIG 1 - `endif - `endif - - `ifdef TX_QUAD - `define TX_EN_0 - `define TX_EN_1 - `define TX_EN_2 - `define TX_EN_3 - `ifdef TX_DIG_ON - `define TX_EN_DIG_0 - `define TX_EN_DIG_1 - `define TX_CAP_DIG 1 - `endif - `define TX_CAP_NCHAN 3'd4 - `endif - - `ifdef TX_HB_ON - `define TX_CAP_HB 1 - `else - `define TX_CAP_HB 0 - `endif - -`else // !ifdef TX_ON - - `define TX_CAP_NCHAN 3'd0 - `define TX_CAP_HB 0 - -`endif // !ifdef TX_ON - -// -------------------------------------------------------------------- - -`ifdef RX_ON - - `ifdef RX_SINGLE - `define RX_EN_0 - `define RX_CAP_NCHAN 3'd1 - `ifdef RX_DIG_ON - `define RX_EN_DIG_0 - `define RX_CAP_DIG 1 - `endif - `endif - - `ifdef RX_DUAL - `define RX_EN_0 - `define RX_EN_1 - `define RX_CAP_NCHAN 3'd2 - `ifdef RX_DIG_ON - `define RX_EN_DIG_0 - `define RX_EN_DIG_1 - `define RX_CAP_DIG 1 - `endif - `endif - - `ifdef RX_QUAD - `define RX_EN_0 - `define RX_EN_1 - `define RX_EN_2 - `define RX_EN_3 - `define RX_CAP_NCHAN 3'd4 - `ifdef RX_DIG_ON - `define RX_EN_DIG_0 - `define RX_EN_DIG_1 - `define RX_CAP_DIG 1 - `endif - `endif - - `ifdef RX_HB_ON - `define RX_CAP_HB 1 - `else - `define RX_CAP_HB 0 - `endif - -`else // !ifdef RX_ON - - `define RX_CAP_NCHAN 3'd0 - `define RX_CAP_HB 0 - -`endif // !ifdef RX_ON diff --git a/gr-gpio/src/fpga/lib/.gitignore b/gr-gpio/src/fpga/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/fpga/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/fpga/lib/Makefile.am b/gr-gpio/src/fpga/lib/Makefile.am deleted file mode 100644 index 85fec113f..000000000 --- a/gr-gpio/src/fpga/lib/Makefile.am +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = - -EXTRA_DIST += \ - gpio_input.v \ - io_pins.v \ - rx_chain_dig.v \ - tx_chain_dig.v \ - integrator.v \ - integ_shifter.v \ - rx_chain.v
\ No newline at end of file diff --git a/gr-gpio/src/fpga/lib/gpio_input.v b/gr-gpio/src/fpga/lib/gpio_input.v deleted file mode 100644 index 871fe3263..000000000 --- a/gr-gpio/src/fpga/lib/gpio_input.v +++ /dev/null @@ -1,80 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module gpio_input - (input clock, input reset, input enable, - input out_strobe, - input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe, - input wire [15:0] io_rx_a_in, input wire [15:0] io_rx_b_in, - //input wire [15:0] io_tx_a_in, input wire [15:0] io_tx_b_in, - output reg rx_dig0_i, output reg rx_dig0_q, - output reg rx_dig1_i, output reg rx_dig1_q ); - - // Buffer at input to chip - - reg rx_dig_rx_a_a,rx_dig_rx_b_a,rx_dig_rx_a_b,rx_dig_rx_b_b; - //TODO possibly use a flancter here - //This code can optionally be extended to do streaming input from gpio of tx boards - //The code can also be extended to input more bits - - always @(posedge clock) - begin - //This is the first point where is determined which physical input gpio pins are used for streaming digital input - //The other point is the code which overrides these pins as input (oe = 0) - //rx_dig_tx_a_a <= #1 io_tx_a_in[14]; - //rx_dig_tx_b_a <= #1 io_tx_a_in[15]; - rx_dig_rx_a_a <= #1 io_rx_a_in[14]; - rx_dig_rx_b_a <= #1 io_rx_a_in[15]; - //rx_dig_tx_a_b <= #1 io_tx_b_in[14]; - //rx_dig_tx_b_b <= #1 io_tx_b_in[15]; - rx_dig_rx_a_b <= #1 io_rx_b_in[14]; - rx_dig_rx_b_b <= #1 io_rx_b_in[15]; - end - - // Now mux to the appropriate outputs - wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux; - wire rx_realsignals; - wire [3:0] rx_numchan;//not used here - //TODO This setting reg readout is a duplicate of the one in adc_interface.v. - // Change code so this is done in only one place, or give this code its own register. - setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr), - .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]})); - //assign rx_numchan[0] = 1'b0; - - always @(posedge clock) - if (out_strobe) //out_strobe determines the time at which the digital inputs are sampled (with a delay of one sample) - begin - rx_dig0_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig0_q <= #1 rx_realsignals ? 1'b0 : ddc0mux[3] ? (ddc0mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig1_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig1_q <= #1 rx_realsignals ? 1'b0 : ddc1mux[3] ? (ddc1mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig2_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig2_q <= #1 rx_realsignals ? 1'b0 : ddc2mux[3] ? (ddc2mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig3_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig3_q <= #1 rx_realsignals ? 1'b0 : ddc3mux[3] ? (ddc3mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - end - -endmodule // gpio_input - - diff --git a/gr-gpio/src/fpga/lib/integ_shifter.v b/gr-gpio/src/fpga/lib/integ_shifter.v deleted file mode 100644 index 1ad0504cb..000000000 --- a/gr-gpio/src/fpga/lib/integ_shifter.v +++ /dev/null @@ -1,68 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// NOTE: This only works for a max decim rate of 256 -// NOTE: Signal "rate" is ONE LESS THAN the actual rate - -module integ_shifter(rate,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 8; - - input [7:0] rate; - input wire [bw+maxbitgain-1:0] signal_in; - output reg [bw-1:0] signal_out; - - reg [3:0] bitgain; - - // Nearest without overflow -- ceil(log2(rate+1)) - always @* - if (rate >= 8'd128) - bitgain = 8; - else if (rate >= 8'd64) - bitgain = 7; - else if (rate >= 8'd32) - bitgain = 6; - else if (rate >= 8'd16) - bitgain = 5; - else if (rate >= 8'd8) - bitgain = 4; - else if (rate >= 8'd4) - bitgain = 3; - else if (rate >= 8'd2) - bitgain = 2; - else - bitgain = 1; - - always @* - case(bitgain) - 5'd1 : signal_out = signal_in[1+bw-1:1]; - 5'd2 : signal_out = signal_in[2+bw-1:2]; - 5'd3 : signal_out = signal_in[3+bw-1:3]; - 5'd4 : signal_out = signal_in[4+bw-1:4]; - 5'd5 : signal_out = signal_in[5+bw-1:5]; - 5'd6 : signal_out = signal_in[6+bw-1:6]; - 5'd7 : signal_out = signal_in[7+bw-1:7]; - default : signal_out = signal_in[8+bw-1:8]; - endcase // case(shift) - -endmodule // integ_shifter diff --git a/gr-gpio/src/fpga/lib/integrator.v b/gr-gpio/src/fpga/lib/integrator.v deleted file mode 100644 index 22357a565..000000000 --- a/gr-gpio/src/fpga/lib/integrator.v +++ /dev/null @@ -1,75 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Integrate and dump decimation filter -// -// Functionally equivalent to single-stage CIC decimator, simpler code -// Results in single sample impulse response at decimated rate - -module integrator - ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 8; - - input clock; - input reset; - input enable; - input [7:0] rate; - input strobe_in; - input strobe_out; - - input [bw-1:0] signal_in; - wire [bw-1:0] signal_out_unreg; - output [bw-1:0] signal_out; - reg [bw-1:0] signal_out; - - wire [bw+maxbitgain-1:0] signal_in_ext; - reg [bw+maxbitgain-1:0] accum; - reg [bw+maxbitgain-1:0] dump; - - sign_extend #(bw,bw+maxbitgain) - ext_input (.in(signal_in),.out(signal_in_ext)); - - // Integrate samples, dump on strobe out - always @(posedge clock) - if (reset | ~enable) - begin - accum <= 0; - dump <= 0; - end - else if (enable && strobe_in) - if (~strobe_out) - accum <= accum + signal_in_ext; - else - begin - dump <= accum; - accum <= signal_in_ext; - end - - // Normalize for integration bit gain - integ_shifter #(bw) - shifter(rate,dump,signal_out_unreg); - - always @(posedge clock) - signal_out <= #1 signal_out_unreg; - -endmodule // integrator diff --git a/gr-gpio/src/fpga/lib/io_pins.v b/gr-gpio/src/fpga/lib/io_pins.v deleted file mode 100644 index 9d857902f..000000000 --- a/gr-gpio/src/fpga/lib/io_pins.v +++ /dev/null @@ -1,55 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2005,2006 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module io_pins - ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, - input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, - input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output, - input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input, - input clock, input rx_reset, input tx_reset, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); - - reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; - - bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe | io_0_force_output),.reg_val(reg_0)); - bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe & (~io_1_force_input)),.reg_val(reg_1)); - bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe | io_2_force_output),.reg_val(reg_2)); - bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe & (~io_3_force_input)),.reg_val(reg_3)); - - // Upper 16 bits are mask for lower 16 - always @(posedge clock) - if(serial_strobe) - case(serial_addr) - `FR_OE_0 : io_0_oe - <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_1 : io_1_oe - <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_2 : io_2_oe - <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_3 : io_3_oe - <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - endcase // case(serial_addr) - -endmodule // io_pins diff --git a/gr-gpio/src/fpga/lib/rx_chain.v b/gr-gpio/src/fpga/lib/rx_chain.v deleted file mode 100644 index 172e978de..000000000 --- a/gr-gpio/src/fpga/lib/rx_chain.v +++ /dev/null @@ -1,121 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Following defines conditionally include RX path circuitry - -`include "config.vh" // resolved relative to project root - -module rx_chain - (input clock, - input reset, - input enable, - input wire [7:0] decim_rate, - input sample_strobe, - input decimator_strobe, - output wire hb_strobe, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out, - output wire [15:0] q_out, - output wire [15:0] debugdata,output wire [15:0] debugctrl - ); - - parameter FREQADDR = 0; - parameter PHASEADDR = 0; - - wire [31:0] phase; - wire [15:0] bb_i, bb_q; - wire [15:0] hb_in_i, hb_in_q; - - assign debugdata = hb_in_i; - -`ifdef RX_NCO_ON - phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc - (.clk(clock),.reset(reset),.enable(enable), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .strobe(sample_strobe),.phase(phase) ); - - cordic rx_cordic - ( .clock(clock),.reset(reset),.enable(enable), - .xi(i_in),.yi(q_in),.zi(phase[31:16]), - .xo(bb_i),.yo(bb_q),.zo() ); -`else - assign bb_i = i_in; - assign bb_q = q_in; - assign sample_strobe = 1; -`endif // !`ifdef RX_NCO_ON - -`ifdef RX_INTEG_ON - integrator integ_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i),.signal_out(i_out) ); - - assign hb_strobe = decimator_strobe; -`else -`ifdef RX_CIC_ON - cic_decim cic_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i),.signal_out(hb_in_i) ); -`else - assign hb_in_i = bb_i; - assign decimator_strobe = sample_strobe; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(hb_strobe), - .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) ); -`else - assign i_out = hb_in_i; - assign hb_strobe = decimator_strobe; -`endif -`endif // RX_INTEG_ON - -`ifdef RX_INTEG_ON - integrator integ_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q),.signal_out(q_out) ); -`else -`ifdef RX_CIC_ON - cic_decim cic_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q),.signal_out(hb_in_q) ); -`else - assign hb_in_q = bb_q; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(), - .data_in(hb_in_q),.data_out(q_out) ); -`else - assign q_out = hb_in_q; -`endif -`endif // RX_INTEG_ON - -endmodule // rx_chain diff --git a/gr-gpio/src/fpga/lib/rx_chain_dig.v b/gr-gpio/src/fpga/lib/rx_chain_dig.v deleted file mode 100644 index 4f760dded..000000000 --- a/gr-gpio/src/fpga/lib/rx_chain_dig.v +++ /dev/null @@ -1,43 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Following defines conditionally include RX path circuitry - -`include "../top/config.vh" // resolved relative to project root - -module rx_chain_dig - (input clock, - input reset, - input enable, - input wire [15:0] i_in_ana, - input wire [15:0] q_in_ana, - input wire i_in_dig, - input wire q_in_dig, - output wire [15:0] i_out, - output wire [15:0] q_out - ); - - //assign upper 15 bits of output to analog input, - // discards lsb of analog input and replace with digital input bit (which comes from gpio) - assign i_out = (enable)?{i_in_ana[15:1],i_in_dig}:i_in_ana; - assign q_out = (enable)?{q_in_ana[15:1],q_in_dig}:q_in_ana; - -endmodule // rx_chain_dig diff --git a/gr-gpio/src/fpga/lib/tx_chain_dig.v b/gr-gpio/src/fpga/lib/tx_chain_dig.v deleted file mode 100644 index 7001947f7..000000000 --- a/gr-gpio/src/fpga/lib/tx_chain_dig.v +++ /dev/null @@ -1,42 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module tx_chain_dig - (input clock, - input reset, - input enable, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out_ana, - output wire [15:0] q_out_ana, - output wire i_out_dig, - output wire q_out_dig - ); - - //assign upper 15 bits to analog processing, discard lowest bit - //output lower two bits of I and Q as digital signal (to be output on gpio pins) - assign i_out_ana = (enable)?{i_in[15:1],1'b0}:i_in; - assign q_out_ana = (enable)?{q_in[15:1],1'b0}:q_in; - //wire out_dig = (enable)?{i_in[0],q_in[0]}:2'b00; - assign i_out_dig = (enable)?i_in[0]:1'b0; - assign q_out_dig = (enable)?q_in[0]:1'b0; - -endmodule // tx_chain_dig diff --git a/gr-gpio/src/fpga/rbf/.gitignore b/gr-gpio/src/fpga/rbf/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/fpga/rbf/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/fpga/rbf/Makefile.am b/gr-gpio/src/fpga/rbf/Makefile.am deleted file mode 100644 index e444d62eb..000000000 --- a/gr-gpio/src/fpga/rbf/Makefile.am +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright 2008,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -RBFS = \ - std_2rxhb_2tx_dig.rbf \ - std_2rxint_2tx_dig.rbf - -datadir = $(prefix)/share/usrp -datarev2dir = $(datadir)/rev2 -datarev4dir = $(datadir)/rev4 - -dist_datarev2_DATA = $(RBFS) - -dist_datarev4_DATA = $(RBFS) diff --git a/gr-gpio/src/fpga/rbf/std_2rxhb_2tx_dig.rbf b/gr-gpio/src/fpga/rbf/std_2rxhb_2tx_dig.rbf Binary files differdeleted file mode 100644 index 5d1c9c7d2..000000000 --- a/gr-gpio/src/fpga/rbf/std_2rxhb_2tx_dig.rbf +++ /dev/null diff --git a/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf b/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf Binary files differdeleted file mode 100644 index 60e194eee..000000000 --- a/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf +++ /dev/null diff --git a/gr-gpio/src/fpga/top/.gitignore b/gr-gpio/src/fpga/top/.gitignore deleted file mode 100644 index 28be78cfc..000000000 --- a/gr-gpio/src/fpga/top/.gitignore +++ /dev/null @@ -1,11 +0,0 @@ -/Makefile -/Makefile.in -/db -/prev*.* -/*.summary -/*.qws -/*.rpt -/*.done -/*.pin -/*.sof -/*.rbf diff --git a/gr-gpio/src/fpga/top/Makefile.am b/gr-gpio/src/fpga/top/Makefile.am deleted file mode 100644 index 34b00076c..000000000 --- a/gr-gpio/src/fpga/top/Makefile.am +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright 2008,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - config.vh \ - usrp_gpio.csf \ - usrp_gpio.esf \ - usrp_gpio.psf \ - usrp_gpio.qpf \ - usrp_gpio.qsf \ - usrp_gpio.v - -MOSTLYCLEANFILES += \ - db/* \ - *.rpt \ - *.summary \ - *.qws \ - *.smsg \ - *.done \ - *.pin \ - *.sof diff --git a/gr-gpio/src/fpga/top/config.vh b/gr-gpio/src/fpga/top/config.vh deleted file mode 100644 index d40e75d2f..000000000 --- a/gr-gpio/src/fpga/top/config.vh +++ /dev/null @@ -1,60 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// Uncomment only ONE configuration -// ==================================================================== - -// ==================================================================== -// FIXME drive configuration selection from the command line and/or gui -// ==================================================================== - -// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel -//`include "../include/common_config_1rxhb_1tx.vh" - -// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels -//`include "../include/common_config_2rxhb_2tx.vh" - -// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels with digital output (lsb of I and Q) on gpio pins -//`include "../include/common_config_2rxhb_2tx_dig.vh" - -// Uncomment this for 2 rx channels (w/o halfband, but w/integrator) & 2 tx channels, with streaming GPIO - `include "../include/common_config_2rxint_2tx_dig.vh" - -// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_4rx_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels -//`include "../include/common_config_2rxhb_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_2rx_0tx.vh" - -// Add other "known to fit" configurations here... - -// ==================================================================== -// Now include the common footer -// ==================================================================== - `include "../include/common_config_bottom.vh" diff --git a/gr-gpio/src/fpga/top/usrp_gpio.csf b/gr-gpio/src/fpga/top/usrp_gpio.csf deleted file mode 100644 index 8a6a0b466..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_gpio; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_gpio) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/gr-gpio/src/fpga/top/usrp_gpio.esf b/gr-gpio/src/fpga/top/usrp_gpio.esf deleted file mode 100644 index 5ca386649..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_gpio; -} diff --git a/gr-gpio/src/fpga/top/usrp_gpio.psf b/gr-gpio/src/fpga/top/usrp_gpio.psf deleted file mode 100644 index ff8e6ab08..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_gpio) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_gpio) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>"; - EDA_SIMULATION_TOOL = "<NONE>"; - EDA_TIMING_ANALYSIS_TOOL = "<NONE>"; - EDA_BOARD_DESIGN_TOOL = "<NONE>"; - EDA_FORMAL_VERIFICATION_TOOL = "<NONE>"; - EDA_RESYNTHESIS_TOOL = "<NONE>"; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qpf b/gr-gpio/src/fpga/top/usrp_gpio.qpf deleted file mode 100644 index 7eb8da9eb..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_gpio" diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qsf b/gr-gpio/src/fpga/top/usrp_gpio.qsf deleted file mode 100644 index cfdcd552b..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.qsf +++ /dev/null @@ -1,412 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# usrp_gpio_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Timing Assignments
-# ==================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_gpio
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# -----------------
-# start CLOCK(SCLK)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# -----------------------
-# start CLOCK(master_clk)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# -------------------
-# start CLOCK(usbclk)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# ----------------------
-# start ENTITY(usrp_gpio)
-
- # Timing Assignments
- # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-# end ENTITY(usrp_gpio)
-# --------------------
-
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name VERILOG_FILE usrp_gpio.v
-set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v
-set_global_assignment -name VERILOG_FILE ../lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v
-set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v
-set_global_assignment -name VERILOG_FILE ../lib/integrator.v
-set_global_assignment -name VERILOG_FILE ../lib/integ_shifter.v
-set_global_assignment -name VERILOG_FILE ../lib/rx_chain.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/bustri.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/fifo_4k_18.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v
\ No newline at end of file diff --git a/gr-gpio/src/fpga/top/usrp_gpio.v b/gr-gpio/src/fpga/top/usrp_gpio.v deleted file mode 100644 index 50a0dbe64..000000000 --- a/gr-gpio/src/fpga/top/usrp_gpio.v +++ /dev/null @@ -1,467 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins -// for debugging info. NB, This can kill the m'board and/or d'board if you -// have anything except basic d'boards installed. - -// Uncomment the following to include optional circuitry - -`include "../top/config.vh" -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module usrp_gpio -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64,clk128; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - wire [2:0] tx_numchan; - - wire [7:0] interp_rate, decim_rate; - wire [31:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - wire [15:0] ch0rx_ext,ch1rx_ext; - - // TX - wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;//analog signals - wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; - - wire strobe_interp, tx_sample_strobe; - wire tx_empty; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - reg [15:0] debug_counter; - reg [15:0] loopback_i_0,loopback_q_0; - - //TX_DIG streaming digital IO signals - wire i_out_dig_0,i_out_dig_1,q_out_dig_0,q_out_dig_1; - wire rx_dig0_i, rx_dig0_q,rx_dig1_i,rx_dig1_q; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side -`ifdef TX_ON - - tx_buffer tx_buffer - ( .usbclk(usbclk), .bus_reset(tx_bus_reset), - .usbdata(usbdata),.WR(WR), .have_space(have_space), - .tx_underrun(tx_underrun), .clear_status(clear_status), - .txclk(clk64), .reset(tx_dsp_reset), - .channels({tx_numchan,1'b0}), - .tx_i_0(ch0tx),.tx_q_0(ch1tx), - .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .txstrobe(strobe_interp), - .tx_empty(tx_empty), - .debugbus(tx_debugbus) ); - - `ifdef TX_EN_0 - tx_chain tx_chain_0 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0)); - `else - assign i_out_0=16'd0; - assign q_out_0=16'd0; - `endif - - `ifdef TX_EN_1 - tx_chain tx_chain_1 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); - `else - assign i_out_1=16'd0; - assign q_out_1=16'd0; - `endif - - - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; - - wire tx_dig_a_a = (dac0mux[1] ? (dac0mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac0mux[0] ? q_out_dig_0 : i_out_dig_0)); - wire tx_dig_b_a = (dac1mux[1] ? (dac1mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac1mux[0] ? q_out_dig_0 : i_out_dig_0)); - wire tx_dig_a_b = (dac2mux[1] ? (dac2mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac2mux[0] ? q_out_dig_0 : i_out_dig_0)); - wire tx_dig_b_b = (dac3mux[1] ? (dac3mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac3mux[0] ? q_out_dig_0 : i_out_dig_0)); - - //wire [1:0] tx_dig_a = {tx_dig_a_a,tx_dig_b_a}; - //wire [1:0] tx_dig_b = {tx_dig_a_b,tx_dig_b_b}; - - //wire tx_dig_a_chan = (dac0mux[1] | dac1mux[1] ); - //wire tx_dig_b_chan = (dac2mux[1] | dac3mux[1] ); - - //TODO make enabling tx_dig configurable through register - - wire enable_tx_dig_a = 1'b1 & enable_tx; - wire enable_tx_dig_b = 1'b1 & enable_tx; - - wire tx_dig_a_a_en = dac0mux[3] & enable_tx_dig_a; - wire tx_dig_b_a_en = dac1mux[3] & enable_tx_dig_a; - wire tx_dig_a_b_en = dac2mux[3] & enable_tx_dig_b; - wire tx_dig_b_b_en = dac3mux[3] & enable_tx_dig_b; - - //TODO make gpio bits used for tx_dig configurable through register - assign io_tx_a_out = {tx_dig_a_a_en?tx_dig_a_a:reg_0[15],tx_dig_b_a_en?tx_dig_b_a:reg_0[14],reg_0[13:0]}; - assign io_tx_b_out = {tx_dig_a_b_en?tx_dig_a_b:reg_2[15],tx_dig_b_b_en?tx_dig_b_b:reg_2[14],reg_2[13:0]}; - assign io_tx_a_force_output = {tx_dig_a_a_en,tx_dig_b_a_en,14'b0}; - assign io_tx_b_force_output = {tx_dig_a_b_en,tx_dig_b_b_en,14'b0}; - - - `ifdef TX_EN_DIG_0 - //TODO make enabling tx_dig configurable through register - //tx_chain_dig tx_chain_dig_0 - // ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - // .i_in(ch0tx), q_in(ch1tx), - // .i_out_ana(bb_tx_i0), - // .q_out_ana(bb_tx_q0), - // .i_out_dig(i_out_dig_0), - // .q_out_dig(q_out_dig_0) - // ); - tx_chain_dig tx_chain_dig_0 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .i_in(ch0tx),.q_in(ch1tx), - .i_out_ana(bb_tx_i0),.q_out_ana(bb_tx_q0), - .i_out_dig(i_out_dig_0),.q_out_dig(q_out_dig_0)); - `else - assign bb_tx_i0 = ch0tx; - assign bb_tx_q0 = ch1tx; - assign i_out_dig_0=1'b0; - assign q_out_dig_0=1'b0; - `endif - - `ifdef TX_EN_DIG_1 - //TODO make enabling tx_dig configurable through register - tx_chain_dig tx_chain_dig_1 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .i_in(ch2tx),.q_in(ch3tx), - .i_out_ana(bb_tx_i1),.q_out_ana(bb_tx_q1), - .i_out_dig(i_out_dig_1),.q_out_dig(q_out_dig_1)); -// tx_chain_dig tx_chain_dig_1 -// ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), -// .i_in(ch2tx), q_in(ch3tx), -// .i_out_ana(bb_tx_i1), -// .q_out_ana(bb_tx_q1), -// .i_out_dig(i_out_dig_1), -// .q_out_dig(q_out_dig_1) -// ); - `else - assign bb_tx_i1 = ch2tx; - assign bb_tx_q1 = ch3tx; - assign i_out_dig_1=1'b0; - assign q_out_dig_1=1'b0; - `endif - - wire txsync = tx_sample_strobe; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; - assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; -`else // `ifdef TX_ON - assign io_tx_a_out = reg_0; - assign io_tx_b_out = reg_2; - assign io_tx_a_force_output=16'b0; - assign io_tx_b_force_output=16'b0; -`endif - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side -`ifdef RX_ON - wire rx_sample_strobe,strobe_decim,hb_strobe; - wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, - bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; - - wire loopback = settings[0]; - wire counter = settings[1]; - - always @(posedge clk64) - if(rx_dsp_reset) - debug_counter <= #1 16'd0; - else if(~enable_rx) - debug_counter <= #1 16'd0; - else if(hb_strobe) - debug_counter <=#1 debug_counter + 16'd2; - - always @(posedge clk64) - if(strobe_interp) - begin - loopback_i_0 <= #1 ch0tx; - loopback_q_0 <= #1 ch1tx; - end - - - wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; - wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; - - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), - .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), - .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), - .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), - .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(ch0rx_ext),.ch_1(ch1rx_ext), - .ch_2(ch2rx),.ch_3(ch3rx), - .ch_4(ch4rx),.ch_5(ch5rx), - .ch_6(ch6rx),.ch_7(ch7rx), - .rxclk(clk64),.rxstrobe(hb_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); - - `ifdef RX_EN_0 - rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); - `else - assign bb_rx_i0=16'd0; - assign bb_rx_q0=16'd0; - `endif - - `ifdef RX_EN_1 - rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); - `else - assign bb_rx_i1=16'd0; - assign bb_rx_q1=16'd0; - `endif - - `ifdef RX_EN_2 - rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); - `else - assign bb_rx_i2=16'd0; - assign bb_rx_q2=16'd0; - `endif - - `ifdef RX_EN_3 - rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); - `else - assign bb_rx_i3=16'd0; - assign bb_rx_q3=16'd0; - `endif - - `ifdef RX_DIG_ON - wire enable_rx_dig = 1'b1 & enable_rx;//TODO make enabling rx_dig configurable through register - assign io_rx_a_force_input = {enable_rx_dig,enable_rx_dig,14'b0}; - assign io_rx_b_force_input = {enable_rx_dig,enable_rx_dig,14'b0}; - gpio_input gpio_input(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), - .out_strobe(hb_strobe), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .io_rx_a_in(io_rx_a),.io_rx_b_in(io_rx_b), - //.io_tx_a_in(io_tx_a),.io_tx_b_in(io_tx_b), - .rx_dig0_i(rx_dig0_i),.rx_dig0_q(rx_dig0_q), - .rx_dig1_i(rx_dig1_i),.rx_dig1_q(rx_dig1_q) ); - - `ifdef RX_EN_DIG_0 - rx_chain_dig rx_chain_dig_0 - ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig), - .i_in_ana(bb_rx_i0),.q_in_ana(bb_rx_q0), - .i_in_dig(rx_dig0_i),.q_in_dig(rx_dig0_q), - .i_out(ch0rx),.q_out(ch1rx)); - `else - assign ch0rx = bb_rx_i0; - assign ch1rx = bb_rx_q0; - `endif - - assign ch0rx_ext = counter ? debug_counter : loopback ? loopback_i_0 : ch0rx; - assign ch1rx_ext = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : ch1rx; - - `ifdef RX_EN_DIG_1 - rx_chain_dig rx_chain_dig_1 - ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig), - .i_in_ana(bb_rx_i1),.q_in_ana(bb_rx_q1), - .i_in_dig(rx_dig1_i),.q_in_dig(rx_dig1_q), - .i_out(ch2rx),.q_out(ch3rx)); - `else - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - `endif - - assign ch4rx = bb_rx_i2; - assign ch5rx = bb_rx_q2; - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; - `else // `ifdef RX_DIG_ON - assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; - assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - assign ch4rx = bb_rx_i2; - assign ch5rx = bb_rx_q2; - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; - `endif // `ifdef RX_DIG_ON - -`endif // `ifdef RX_ON - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = `TX_CAP_HB; - assign capabilities[6:4] = `TX_CAP_NCHAN; - assign capabilities[3] = `RX_CAP_HB; - assign capabilities[2:0] = `RX_CAP_NCHAN; - - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) - ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - wire [15:0] io_tx_a_out; - wire [15:0] io_tx_b_out; - wire [15:0] io_tx_a_force_output; - wire [15:0] io_tx_b_force_output; - wire [15:0] io_rx_a_force_input; - wire [15:0] io_rx_b_force_input; - - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), - .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]), - //.tx_dig_a(tx_dig_a),tx_dig_b(tx_dig_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(io_tx_a_out),.reg_1(reg_1),.reg_2(io_tx_b_out),.reg_3(reg_3), - .io_0_force_output(io_tx_a_force_output), .io_2_force_output(io_tx_b_force_output), - .io_1_force_input(io_rx_a_force_input), .io_3_force_input(io_rx_b_force_input), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Misc Settings - setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); - -endmodule // usrp_gpio diff --git a/gr-gpio/src/python/.gitignore b/gr-gpio/src/python/.gitignore deleted file mode 100644 index b9e19a979..000000000 --- a/gr-gpio/src/python/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/Makefile -/Makefile.in -/*.pyc -/run_tests diff --git a/gr-gpio/src/python/Makefile.am b/gr-gpio/src/python/Makefile.am deleted file mode 100644 index 427047cdf..000000000 --- a/gr-gpio/src/python/Makefile.am +++ /dev/null @@ -1,37 +0,0 @@ -# -# Copyright 2007,2008,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -# Installation locations -ourpythondir = $(grpythondir)/gpio -ourlibdir = $(grpyexecdir)/gpio - -# List of Python files that will get installed into site-packages -ourpython_PYTHON = \ - __init__.py \ - gpio.py - -# List of python files that will be installed onto $prefix/bin -dist_bin_SCRIPTS = \ - gpio_rx_sfile.py \ - gpio_usrp_siggen.py \ - gpio_usrp_fft.py diff --git a/gr-gpio/src/python/__init__.py b/gr-gpio/src/python/__init__.py deleted file mode 100644 index b1f69b7ea..000000000 --- a/gr-gpio/src/python/__init__.py +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright 2007,2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -import glob -import os.path - -# This automatically imports all top-level objects from .py files -# in our directory into the package name space -for _p in __path__: - _filenames = glob.glob (os.path.join (_p, "*.py")) - for _f in _filenames: - _f = os.path.basename(_f).lower() - _f = _f[:-3] - if _f == '__init__': - continue - exec "from %s import *" % (_f,) diff --git a/gr-gpio/src/python/gpio.py b/gr-gpio/src/python/gpio.py deleted file mode 100644 index a315e166b..000000000 --- a/gr-gpio/src/python/gpio.py +++ /dev/null @@ -1 +0,0 @@ -fpga_filename = 'std_2rxint_2tx_dig.rbf' diff --git a/gr-gpio/src/python/gpio_rx_sfile.py b/gr-gpio/src/python/gpio_rx_sfile.py deleted file mode 100755 index 31f598ef7..000000000 --- a/gr-gpio/src/python/gpio_rx_sfile.py +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2008,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, eng_notation -from gnuradio import usrp -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import sys - -from gnuradio import gpio - -class my_top_block(gr.top_block): - - def __init__(self, options): - gr.top_block.__init__(self) - - # Create a USRP source with GPIO FPGA build, then configure - u = usrp.source_s(decim_rate=options.decim,fpga_filename=gpio.fpga_filename) - - if options.force_complex_RXA: - # This is a dirty hack to force complex mode (receive both I and Q) on basicRX or LFRX - # This forces the receive board in RXA (side A) to be used - # FIXME: This has as a side effect that the gain for Q is not set. So only use with gain 0 (--gain 0) - options.rx_subdev_spec=(0,0) - u.set_mux(0x10) - if not (0==options.gain): - print "WARNING, you should set the gain to 0 with --gain 0 when using --force-complex-RXA" - print "The gain for Q will now still be zero while the gain for I is not" - #options.gain=0 - else: - if options.rx_subdev_spec is None: - options.rx_subdev_spec = usrp.pick_rx_subdevice(u) - u.set_mux(usrp.determine_rx_mux_value(u, options.rx_subdev_spec)) - - subdev = usrp.selected_subdev(u, options.rx_subdev_spec) - print "Using RX d'board %s" % (subdev.side_and_name(),) - input_rate = u.adc_freq()/u.decim_rate() - print "USB sample rate %s" % (eng_notation.num_to_str(input_rate)) - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - g = subdev.gain_range() - options.gain = float(g[0]+g[1])/2 - - - #TODO setting gain on basicRX only sets the I channel, use a second subdev to set gain of Q channel - #see gnuradio-examples/multi-antenna for possible solutions - subdev.set_gain(options.gain) - - #TODO check if freq has same problem as gain when trying to use complex mode on basicRX - r = u.tune(0, subdev, options.freq) - if not r: - sys.stderr.write('Failed to set frequency\n') - raise SystemExit, 1 - - # Connect pipeline - src = u - if options.nsamples is not None: - head = gr.head(gr.sizeof_short, int(options.nsamples)*2) - self.connect(u, head) - src = head - - ana_strip = gr.and_const_ss(0xFFFE) - dig_strip = gr.and_const_ss(0x0001) - ana_sink = gr.file_sink(gr.sizeof_short, options.ana_filename) - dig_sink = gr.file_sink(gr.sizeof_short, options.dig_filename) - - self.connect(src, ana_strip, ana_sink) - self.connect(src, dig_strip, dig_sink) - -if __name__ == '__main__': - usage="%prog: [options] analog_filename digital_filename" - parser = OptionParser(option_class=eng_option, usage=usage) - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=(0, 0), - help="select USRP Rx side A or B (default=A)") - parser.add_option("-d", "--decim", type="int", default=16, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=None, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-N", "--nsamples", type="eng_float", default=None, - help="number of samples to collect [default=+inf]") - parser.add_option("-F", "--force-complex-RXA", action="store_true", default=False, - help="enable basicRX hack to force complex mode on basicRX and LFRX. Only works on side A. Only use with --gain 0") - (options, args) = parser.parse_args () - if len(args) != 2: - parser.print_help() - raise SystemExit, 1 - options.ana_filename = args[0] - options.dig_filename = args[1] - - if options.freq is None: - parser.print_help() - sys.stderr.write('You must specify the frequency with -f FREQ\n'); - raise SystemExit, 1 - - try: - tb = my_top_block(options) - tb.run() - except KeyboardInterrupt: - pass diff --git a/gr-gpio/src/python/gpio_usrp_fft.py b/gr-gpio/src/python/gpio_usrp_fft.py deleted file mode 100755 index c9ecb032d..000000000 --- a/gr-gpio/src/python/gpio_usrp_fft.py +++ /dev/null @@ -1,333 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2004,2005,2007,2008,2009,2010 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2, form, slider -from optparse import OptionParser -import wx -import sys -import numpy - -from gnuradio import gpio - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem - return (0, 0) - #if u.db[1][0].dbid() >= 0: #disable the use of RXB - # return (1, 0) - return (0, 0) - - -class app_top_block(stdgui2.std_top_block): - def __init__(self, frame, panel, vbox, argv): - stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv) - - self.frame = frame - self.panel = panel - - parser = OptionParser(option_class=eng_option) - parser.add_option("-w", "--which", type="int", default=0, - help="select which USRP (0, 1, ...) default is %default", - metavar="NUM") -# parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, -# help="select USRP Rx side A or B (default=first one with a daughterboard)") - parser.add_option("-A", "--antenna", default=None, - help="select Rx Antenna (only on RFX-series boards)") - parser.add_option("-d", "--decim", type="int", default=32, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=0.0, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-W", "--waterfall", action="store_true", default=False, - help="Enable waterfall display") - parser.add_option("-8", "--width-8", action="store_true", default=False, - help="Enable 8-bit samples across USB") -# parser.add_option( "--no-hb", action="store_true", default=False, -# help="don't use halfband filter in usrp") - parser.add_option("-S", "--oscilloscope", action="store_true", default=False, - help="Enable oscilloscope display (default)") - parser.add_option("-F", "--fft", action="store_true", default=False, - help="Enable FFT display") - parser.add_option("-n", "--frame-decim", type="int", default=1, - help="set oscope frame decimation factor to n [default=1]") - parser.add_option("-v", "--v-scale", type="eng_float", default=1, - help="set oscope initial V/div to SCALE [default=%default]") - parser.add_option("-t", "--t-scale", type="eng_float", default=10e-6, - help="set oscope initial s/div to SCALE [default=10us]") - parser.add_option ("--digital", action="store_true", default=False, - help="show (only) the digital wave on lsb (will be input from gpio pins with special usrp firmware)") - parser.add_option ("--analog", action="store_true", default=False, - help="show (only) the analog wave on msbs (will be input from analog inputs)") - parser.add_option ("--file", default=None, - help="input from file FILE in stead of USRP (will be input from raw file in interleaved short format)") - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - self.options = options - self.show_debug_info = True - - self.u = usrp.source_s(which=options.which, decim_rate=options.decim, fpga_filename=gpio.fpga_filename) - - print "Warning: This script only supports boards on RXA, change the script if you want otherwise" - #options.rx_subdev_spec=(0, 0)#force the use of RXA - options.rx_subdev_spec=None #force the use of RXA - - if options.rx_subdev_spec is None: - options.rx_subdev_spec = pick_subdevice(self.u) - - #This hardcoded mux setting is why this script only supports RXA - #We want both I and Q active, even when using basicRX - #set to 0x10 for RXA - #set to 0x32 for RXB - self.u.set_mux(0x10) #usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) - - if options.width_8: - width = 8 - shift = 8 - format = self.u.make_format(width, shift) - print "format =", hex(format) - r = self.u.set_format(format) - print "set_format =", r - - # determine the daughterboard subdevice we're using - self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) - #if options.rx_subdev_spec==(0,0): - # rx_subdev_spec2=(0,1) - # self.subdev2 = usrp.selected_subdev(self.u, rx_subdev_spec2) - input_rate = self.u.adc_freq() / self.u.decim_rate() - - if options.waterfall: - self.scope = \ - waterfallsink2.waterfall_sink_c (panel, fft_size=1024, sample_rate=input_rate) - elif options.fft: - self.scope = fftsink2.fft_sink_c (panel, fft_size=1024, sample_rate=input_rate) - else: # options.oscilloscope: - #self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate) - self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate, - frame_decim=options.frame_decim, - v_scale=options.v_scale, - t_scale=options.t_scale) - - self.is2c = gr.interleaved_short_to_complex() - if not (options.file is None): - self.filesrc=gr.file_source(gr.sizeof_short, options.file, True) - thr = gr.throttle(gr.sizeof_short, input_rate) - self.connect(self.filesrc,thr,self.is2c,self.scope) - elif options.digital: - self.select_dig=gr.and_const_ss(0x0001) - self.connect(self.u, self.select_dig,self.is2c,self.scope) - elif options.analog: - self.select_ana=gr.and_const_ss(0xFFFE) - self.connect(self.u, self.select_ana,self.is2c,self.scope) - else: - self.connect(self.u,self.is2c,self.scope) - - self._build_gui(vbox) - self._setup_events() - - # set initial values - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - g = self.subdev.gain_range() - options.gain = float(g[0]+g[1])/2 - - if options.freq is None: - # if no freq was specified, use the mid-point - r = self.subdev.freq_range() - options.freq = float(r[0]+r[1])/2 - - self.set_gain(options.gain) - - if options.antenna is not None: - print "Selecting antenna %s" % (options.antenna,) - self.subdev.select_rx_antenna(options.antenna) - - if self.show_debug_info: - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - self.myform['dbname'].set_value(self.subdev.name()) - self.myform['baseband'].set_value(0) - self.myform['ddc'].set_value(0) - - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - - def _set_status_msg(self, msg): - self.frame.GetStatusBar().SetStatusText(msg, 0) - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - vbox.Add(self.scope.win, 10, wx.EXPAND) - - # add control area at the bottom - self.myform = myform = form.form() - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0, 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Center freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0, 0) - g = self.subdev.gain_range() - myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, - min=int(g[0]), max=int(g[1]), - callback=self.set_gain) - - hbox.Add((5,0), 0, 0) - vbox.Add(hbox, 0, wx.EXPAND) - - self._build_subpanel(vbox) - - def _build_subpanel(self, vbox_arg): - # build a secondary information panel (sometimes hidden) - - # FIXME figure out how to have this be a subpanel that is always - # created, but has its visibility controlled by foo.Show(True/False) - - def _form_set_decim(kv): - return self.set_decim(kv['decim']) - - if not(self.show_debug_info): - return - - panel = self.panel - vbox = vbox_arg - myform = self.myform - - #panel = wx.Panel(self.panel, -1) - #vbox = wx.BoxSizer(wx.VERTICAL) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - - myform['decim'] = form.int_field( - parent=panel, sizer=hbox, label="Decim", - callback=myform.check_input_and_call(_form_set_decim, self._set_status_msg)) - - hbox.Add((5,0), 1) - myform['fs@usb'] = form.static_float_field( - parent=panel, sizer=hbox, label="Fs@USB") - - hbox.Add((5,0), 1) - myform['dbname'] = form.static_text_field( - parent=panel, sizer=hbox) - - hbox.Add((5,0), 1) - myform['baseband'] = form.static_float_field( - parent=panel, sizer=hbox, label="Analog BB") - - hbox.Add((5,0), 1) - myform['ddc'] = form.static_float_field( - parent=panel, sizer=hbox, label="DDC") - - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - r = self.u.tune(0, self.subdev, target_freq) - - if r: - self.myform['freq'].set_value(target_freq) # update displayed value - if self.show_debug_info: - self.myform['baseband'].set_value(r.baseband_freq) - self.myform['ddc'].set_value(r.dxc_freq) - if not self.options.waterfall and not self.options.oscilloscope: - self.scope.set_baseband_freq(target_freq) - return True - - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - self.subdev.set_gain(gain) - - def set_decim(self, decim): - ok = self.u.set_decim_rate(decim) - if not ok: - print "set_decim failed" - input_rate = self.u.adc_freq() / self.u.decim_rate() - self.scope.set_sample_rate(input_rate) - if self.show_debug_info: # update displayed values - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - return ok - - def _setup_events(self): - if not self.options.waterfall and not self.options.oscilloscope: - self.scope.win.Bind(wx.EVT_LEFT_DCLICK, self.evt_left_dclick) - - def evt_left_dclick(self, event): - (ux, uy) = self.scope.win.GetXY(event) - if event.CmdDown(): - # Re-center on maximum power - points = self.scope.win._points - if self.scope.win.peak_hold: - if self.scope.win.peak_vals is not None: - ind = numpy.argmax(self.scope.win.peak_vals) - else: - ind = int(points.shape()[0]/2) - else: - ind = numpy.argmax(points[:,1]) - (freq, pwr) = points[ind] - target_freq = freq/self.scope.win._scale_factor - print ind, freq, pwr - self.set_freq(target_freq) - else: - # Re-center on clicked frequency - target_freq = ux/self.scope.win._scale_factor - self.set_freq(target_freq) - - -def main (): - app = stdgui2.stdapp(app_top_block, "USRP FFT", nstatus=1) - app.MainLoop() - -if __name__ == '__main__': - main () diff --git a/gr-gpio/src/python/gpio_usrp_siggen.py b/gr-gpio/src/python/gpio_usrp_siggen.py deleted file mode 100755 index 0e483c35d..000000000 --- a/gr-gpio/src/python/gpio_usrp_siggen.py +++ /dev/null @@ -1,208 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# -from gnuradio import gr, gru -from gnuradio import usrp -from gnuradio.eng_option import eng_option -from gnuradio import eng_notation -from optparse import OptionParser -import sys - -from gnuradio import gpio - -class my_top_block(gr.top_block): - def __init__ (self): - gr.top_block.__init__(self) - - # controllable values - self.interp = 64 - self.waveform_type = gr.GR_CONST_WAVE - self.waveform_ampl = 16000 - self.waveform_freq = 100.12345e3 - self.waveform_offset = 0 - self._instantiate_blocks () - self.set_waveform_type (self.waveform_type) - - def usb_freq (self): - return self.u.dac_freq() / self.interp - - def usb_throughput (self): - return self.usb_freq () * 4 - - def set_waveform_type (self, type): - ''' - valid waveform types are: gr.GR_SIN_WAVE, gr.GR_CONST_WAVE, - gr.GR_UNIFORM and gr.GR_GAUSSIAN - ''' - self._configure_graph (type) - self.waveform_type = type - - def set_waveform_ampl (self, ampl): - self.waveform_ampl = ampl - self.siggen.set_amplitude (ampl) - self.noisegen.set_amplitude (ampl) - - def set_waveform_freq (self, freq): - self.waveform_freq = freq - self.siggen.set_frequency (freq) - - def set_waveform_offset (self, offset): - self.waveform_offset = offset - self.siggen.set_offset (offset) - - def set_interpolator (self, interp): - self.interp = interp - self.siggen.set_sampling_freq (self.usb_freq ()) - self.u.set_interp_rate (interp) - - def _instantiate_blocks (self): - self.src = None - self.u = usrp.sink_c (0, self.interp,fpga_filename=gpio.fpga_filename) - - self.siggen = gr.sig_source_c (self.usb_freq (), - gr.GR_SIN_WAVE, - self.waveform_freq, - self.waveform_ampl, - self.waveform_offset) - - self.noisegen = gr.noise_source_c (gr.GR_UNIFORM, - self.waveform_ampl) - self.vecgen = gr.vector_source_c ([complex(1.0,0.0),complex(0.0,0.0),complex(1.0,1.0),complex(0.0,1.0)],True) - - # self.file_sink = gr.file_sink (gr.sizeof_gr_complex, "siggen.dat") - - def _configure_graph (self, type): - try: - self.lock() - self.disconnect_all () - if type == gr.GR_SIN_WAVE: - self.connect (self.siggen, self.u) - # self.connect (self.siggen, self.file_sink) - self.siggen.set_waveform (type) - self.src = self.siggen - elif type == gr.GR_UNIFORM or type == gr.GR_GAUSSIAN: - self.connect (self.noisegen, self.u) - self.noisegen.set_type (type) - self.src = self.noisegen - elif type == gr.GR_CONST_WAVE: - self.connect (self.vecgen, self.u) - self.src = self.vecgen - else: - raise ValueError, type - finally: - self.unlock() - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital up converter. - """ - r = self.u.tune(self.subdev._which, self.subdev, target_freq) - if r: - #print "r.baseband_freq =", eng_notation.num_to_str(r.baseband_freq) - #print "r.dxc_freq =", eng_notation.num_to_str(r.dxc_freq) - #print "r.residual_freq =", eng_notation.num_to_str(r.residual_freq) - #print "r.inverted =", r.inverted - return True - - return False - - - -def main (): - parser = OptionParser (option_class=eng_option) - parser.add_option ("-T", "--tx-subdev-spec", type="subdev", default=(0, 0), - help="select USRP Tx side A or B") - parser.add_option ("-f", "--rf-freq", type="eng_float", default=None, - help="set RF center frequency to FREQ") - parser.add_option ("-i", "--interp", type="int", default=512, - help="set fgpa interpolation rate to INTERP [default=%default]") - parser.add_option ("--sine", dest="type", action="store_const", const=gr.GR_SIN_WAVE, - help="generate a complex sinusoid [default]", default=gr.GR_SIN_WAVE) - - parser.add_option ("--gaussian", dest="type", action="store_const", const=gr.GR_GAUSSIAN, - help="generate Gaussian random output") - parser.add_option ("--uniform", dest="type", action="store_const", const=gr.GR_UNIFORM, - help="generate Uniform random output") - - parser.add_option ("-w", "--waveform-freq", type="eng_float", default=100e3, - help="set waveform frequency to FREQ [default=%default]") - parser.add_option ("-a", "--amplitude", type="eng_float", default=16e3, - help="set waveform amplitude to AMPLITUDE [default=%default]", metavar="AMPL") - parser.add_option ("-g", "--gain", type="eng_float", default=None, - help="set output gain to GAIN [default=%default]") - parser.add_option ("-o", "--offset", type="eng_float", default=0, - help="set waveform offset to OFFSET [default=%default]") - parser.add_option ("--digital", dest="type", action="store_const", const=gr.GR_CONST_WAVE, - help="generate (only) a digital wave on lsb (will be output on gpio pins with special usrp firmware)") - (options, args) = parser.parse_args () - - if len(args) != 0: - parser.print_help() - raise SystemExit - - if options.rf_freq is None: - sys.stderr.write("usrp_siggen: must specify RF center frequency with -f RF_FREQ\n") - parser.print_help() - raise SystemExit - - tb = my_top_block() - tb.set_interpolator (options.interp) - tb.set_waveform_type (options.type) - tb.set_waveform_freq (options.waveform_freq) - tb.set_waveform_ampl (options.amplitude) - tb.set_waveform_offset (options.offset) - - # determine the daughterboard subdevice we're using - if options.tx_subdev_spec is None: - options.tx_subdev_spec = usrp.pick_tx_subdevice(tb.u) - - m = usrp.determine_tx_mux_value(tb.u, options.tx_subdev_spec) - #print "mux = %#04x" % (m,) - tb.u.set_mux(m) - tb.subdev = usrp.selected_subdev(tb.u, options.tx_subdev_spec) - print "Using TX d'board %s" % (tb.subdev.side_and_name(),) - - if options.gain is None: - tb.subdev.set_gain(tb.subdev.gain_range()[1]) # set max Tx gain - else: - tb.subdev.set_gain(options.gain) # set max Tx gain - - if not tb.set_freq(options.rf_freq): - sys.stderr.write('Failed to set RF frequency\n') - raise SystemExit - - tb.subdev.set_enable(True) # enable transmitter - - try: - tb.run() - except KeyboardInterrupt: - pass - -if __name__ == '__main__': - main () diff --git a/gr-howto-write-a-block/version.sh b/gr-howto-write-a-block/version.sh index 759d52806..83f05bf2b 100644 --- a/gr-howto-write-a-block/version.sh +++ b/gr-howto-write-a-block/version.sh @@ -1,4 +1,4 @@ MAJOR_VERSION=3 -API_COMPAT=4 -MINOR_VERSION=1 -MAINT_VERSION=git +API_COMPAT=5 +MINOR_VERSION=0 +MAINT_VERSION=0 diff --git a/gr-msdd6000/.gitignore b/gr-msdd6000/.gitignore deleted file mode 100644 index a37fc0c1a..000000000 --- a/gr-msdd6000/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/Makefile -/Makefile.in -/*.pc diff --git a/gr-msdd6000/Makefile.am b/gr-msdd6000/Makefile.am deleted file mode 100644 index 89405d08c..000000000 --- a/gr-msdd6000/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = src - -pkgconfigdir = $(libdir)/pkgconfig -dist_pkgconfig_DATA = gnuradio-msdd6000.pc diff --git a/gr-msdd6000/doc/Softronics_Ltd_msdd6000_BlockDiagram.pdf b/gr-msdd6000/doc/Softronics_Ltd_msdd6000_BlockDiagram.pdf Binary files differdeleted file mode 100644 index 34356da75..000000000 --- a/gr-msdd6000/doc/Softronics_Ltd_msdd6000_BlockDiagram.pdf +++ /dev/null diff --git a/gr-msdd6000/gnuradio-msdd6000.pc.in b/gr-msdd6000/gnuradio-msdd6000.pc.in deleted file mode 100644 index 565420718..000000000 --- a/gr-msdd6000/gnuradio-msdd6000.pc.in +++ /dev/null @@ -1,11 +0,0 @@ -prefix=@prefix@ -exec_prefix=@exec_prefix@ -libdir=@libdir@ -includedir=@includedir@ - -Name: gnuradio-comedi -Description: GNU Radio blocks for the Softronics MSDD 6000 -Requires: gnuradio-core -Version: @LIBVER@ -Libs: -L${libdir} -lgnuradio-msdd6000 -Cflags: -I${includedir} diff --git a/gr-msdd6000/src/.gitignore b/gr-msdd6000/src/.gitignore deleted file mode 100644 index 3b0356f86..000000000 --- a/gr-msdd6000/src/.gitignore +++ /dev/null @@ -1,11 +0,0 @@ -/Makefile -/Makefile.in -/.libs -/.deps -/msdd.cc -/msdd.py -/msdd_rs.cc -/msdd_rs.py -/gnuradio -/guile -/python diff --git a/gr-msdd6000/src/Makefile.am b/gr-msdd6000/src/Makefile.am deleted file mode 100644 index 91173702f..000000000 --- a/gr-msdd6000/src/Makefile.am +++ /dev/null @@ -1,79 +0,0 @@ -# -# Copyright 2007,2008,2009,2010 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common -include $(top_srcdir)/Makefile.swig - - -AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES) $(PYTHON_CPPFLAGS) \ - $(WITH_INCLUDES) - -# C/C++ headers get installed in ${prefix}/include/gnuradio -grinclude_HEADERS = \ - msdd_source_simple.h \ - msdd_buffer_copy_behaviors.h \ - msdd6000.h \ - msdd_rs_source_simple.h \ - msdd6000_rs.h - -lib_LTLIBRARIES = libgnuradio-msdd6000.la \ - libgnuradio-msdd6000_rs.la - -libgnuradio_msdd6000_la_LDFLAGS = $(NO_UNDEFINED) $(LTVERSIONFLAGS) -libgnuradio_msdd6000_rs_la_LDFLAGS = $(NO_UNDEFINED) $(LTVERSIONFLAGS) - -libgnuradio_msdd6000_la_SOURCES = \ - msdd_source_simple.cc \ - msdd6000.cc - -libgnuradio_msdd6000_rs_la_SOURCES = \ - msdd_rs_source_simple.cc \ - msdd6000_rs.cc - -libgnuradio_msdd6000_la_LIBADD = \ - $(GNURADIO_CORE_LA) - -libgnuradio_msdd6000_rs_la_LIBADD = \ - $(GNURADIO_CORE_LA) - - -################################# -# SWIG interfaces and libraries - -TOP_SWIG_IFILES = \ - msdd.i msdd_rs.i - -# Install so that they end up available as: -# import gnuradio.msdd -# This ends up at: -# ${prefix}/lib/python${python_version}/site-packages/gnuradio -msdd_pythondir_category = \ - gnuradio - -msdd_rs_pythondir_category = \ - gnuradio - -# additional libraries for linking with the SWIG-generated library -msdd_la_swig_libadd = \ - libgnuradio-msdd6000.la - -msdd_rs_la_swig_libadd = \ - libgnuradio-msdd6000_rs.la diff --git a/gr-msdd6000/src/Makefile.swig.gen b/gr-msdd6000/src/Makefile.swig.gen deleted file mode 100644 index dbf137334..000000000 --- a/gr-msdd6000/src/Makefile.swig.gen +++ /dev/null @@ -1,290 +0,0 @@ -# -*- Makefile -*- -# -# Copyright 2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -# Makefile.swig.gen for msdd.i - -## Default install locations for these files: -## -## Default location for the Python directory is: -## ${prefix}/lib/python${python_version}/site-packages/[category]/msdd -## Default location for the Python exec directory is: -## ${exec_prefix}/lib/python${python_version}/site-packages/[category]/msdd -## -## The following can be overloaded to change the install location, but -## this has to be done in the including Makefile.am -before- -## Makefile.swig is included. - -msdd_pythondir_category ?= gnuradio/msdd -msdd_pylibdir_category ?= $(msdd_pythondir_category) -msdd_pythondir = $(pythondir)/$(msdd_pythondir_category) -msdd_pylibdir = $(pyexecdir)/$(msdd_pylibdir_category) - -# The .so libraries for the guile modules get installed whereever guile -# is installed, usually /usr/lib/guile/gnuradio/ -# FIXME: determince whether these should be installed with gnuradio. -msdd_scmlibdir = $(libdir) - -# The scm files for the guile modules get installed where ever guile -# is installed, usually /usr/share/guile/site/msdd -# FIXME: determince whether these should be installed with gnuradio. -msdd_scmdir = $(guiledir) - -## SWIG headers are always installed into the same directory. - -msdd_swigincludedir = $(swigincludedir) - -## This is a template file for a "generated" Makefile addition (in -## this case, "Makefile.swig.gen"). By including the top-level -## Makefile.swig, this file will be used to generate the SWIG -## dependencies. Assign the variable TOP_SWIG_FILES to be the list of -## SWIG .i files to generated wrappings for; there can be more than 1 -## so long as the names are unique (no sorting is done on the -## TOP_SWIG_FILES list). This file explicitly assumes that a SWIG .i -## file will generate .cc, .py, and possibly .h files -- meaning that -## all of these files will have the same base name (that provided for -## the SWIG .i file). -## -## This code is setup to ensure parallel MAKE ("-j" or "-jN") does the -## right thing. For more info, see < -## http://sources.redhat.com/automake/automake.html#Multiple-Outputs > - -## Other cleaned files: dependency files generated by SWIG or this Makefile - -MOSTLYCLEANFILES += $(DEPDIR)/*.S* - -## Various SWIG variables. These can be overloaded in the including -## Makefile.am by setting the variable value there, then including -## Makefile.swig . - -msdd_swiginclude_HEADERS = \ - msdd.i \ - $(msdd_swiginclude_headers) - -if PYTHON -msdd_pylib_LTLIBRARIES = \ - _msdd.la - -_msdd_la_SOURCES = \ - python/msdd.cc \ - $(msdd_la_swig_sources) - -msdd_python_PYTHON = \ - msdd.py \ - $(msdd_python) - -_msdd_la_LIBADD = \ - $(STD_SWIG_LA_LIB_ADD) \ - $(msdd_la_swig_libadd) - -_msdd_la_LDFLAGS = \ - $(STD_SWIG_LA_LD_FLAGS) \ - $(msdd_la_swig_ldflags) - -_msdd_la_CXXFLAGS = \ - $(STD_SWIG_CXX_FLAGS) \ - -I$(top_builddir) \ - $(msdd_la_swig_cxxflags) - -python/msdd.cc: msdd.py -msdd.py: msdd.i - -# Include the python dependencies for this file --include python/msdd.d - -endif # end of if python - -if GUILE - -msdd_scmlib_LTLIBRARIES = \ - libguile-gnuradio-msdd.la -libguile_gnuradio_msdd_la_SOURCES = \ - guile/msdd.cc \ - $(msdd_la_swig_sources) -nobase_msdd_scm_DATA = \ - gnuradio/msdd.scm \ - gnuradio/msdd-primitive.scm -libguile_gnuradio_msdd_la_LIBADD = \ - $(STD_SWIG_LA_LIB_ADD) \ - $(msdd_la_swig_libadd) -libguile_gnuradio_msdd_la_LDFLAGS = \ - $(STD_SWIG_LA_LD_FLAGS) \ - $(msdd_la_swig_ldflags) -libguile_gnuradio_msdd_la_CXXFLAGS = \ - $(STD_SWIG_CXX_FLAGS) \ - -I$(top_builddir) \ - $(msdd_la_swig_cxxflags) - -guile/msdd.cc: gnuradio/msdd.scm -gnuradio/msdd.scm: msdd.i -gnuradio/msdd-primitive.scm: gnuradio/msdd.scm - -# Include the guile dependencies for this file --include guile/msdd.d - -endif # end of GUILE - - -# -*- Makefile -*- -# -# Copyright 2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -# Makefile.swig.gen for msdd_rs.i - -## Default install locations for these files: -## -## Default location for the Python directory is: -## ${prefix}/lib/python${python_version}/site-packages/[category]/msdd_rs -## Default location for the Python exec directory is: -## ${exec_prefix}/lib/python${python_version}/site-packages/[category]/msdd_rs -## -## The following can be overloaded to change the install location, but -## this has to be done in the including Makefile.am -before- -## Makefile.swig is included. - -msdd_rs_pythondir_category ?= gnuradio/msdd_rs -msdd_rs_pylibdir_category ?= $(msdd_rs_pythondir_category) -msdd_rs_pythondir = $(pythondir)/$(msdd_rs_pythondir_category) -msdd_rs_pylibdir = $(pyexecdir)/$(msdd_rs_pylibdir_category) - -# The .so libraries for the guile modules get installed whereever guile -# is installed, usually /usr/lib/guile/gnuradio/ -# FIXME: determince whether these should be installed with gnuradio. -msdd_rs_scmlibdir = $(libdir) - -# The scm files for the guile modules get installed where ever guile -# is installed, usually /usr/share/guile/site/msdd_rs -# FIXME: determince whether these should be installed with gnuradio. -msdd_rs_scmdir = $(guiledir) - -## SWIG headers are always installed into the same directory. - -msdd_rs_swigincludedir = $(swigincludedir) - -## This is a template file for a "generated" Makefile addition (in -## this case, "Makefile.swig.gen"). By including the top-level -## Makefile.swig, this file will be used to generate the SWIG -## dependencies. Assign the variable TOP_SWIG_FILES to be the list of -## SWIG .i files to generated wrappings for; there can be more than 1 -## so long as the names are unique (no sorting is done on the -## TOP_SWIG_FILES list). This file explicitly assumes that a SWIG .i -## file will generate .cc, .py, and possibly .h files -- meaning that -## all of these files will have the same base name (that provided for -## the SWIG .i file). -## -## This code is setup to ensure parallel MAKE ("-j" or "-jN") does the -## right thing. For more info, see < -## http://sources.redhat.com/automake/automake.html#Multiple-Outputs > - -## Other cleaned files: dependency files generated by SWIG or this Makefile - -MOSTLYCLEANFILES += $(DEPDIR)/*.S* - -## Various SWIG variables. These can be overloaded in the including -## Makefile.am by setting the variable value there, then including -## Makefile.swig . - -msdd_rs_swiginclude_HEADERS = \ - msdd_rs.i \ - $(msdd_rs_swiginclude_headers) - -if PYTHON -msdd_rs_pylib_LTLIBRARIES = \ - _msdd_rs.la - -_msdd_rs_la_SOURCES = \ - python/msdd_rs.cc \ - $(msdd_rs_la_swig_sources) - -msdd_rs_python_PYTHON = \ - msdd_rs.py \ - $(msdd_rs_python) - -_msdd_rs_la_LIBADD = \ - $(STD_SWIG_LA_LIB_ADD) \ - $(msdd_rs_la_swig_libadd) - -_msdd_rs_la_LDFLAGS = \ - $(STD_SWIG_LA_LD_FLAGS) \ - $(msdd_rs_la_swig_ldflags) - -_msdd_rs_la_CXXFLAGS = \ - $(STD_SWIG_CXX_FLAGS) \ - -I$(top_builddir) \ - $(msdd_rs_la_swig_cxxflags) - -python/msdd_rs.cc: msdd_rs.py -msdd_rs.py: msdd_rs.i - -# Include the python dependencies for this file --include python/msdd_rs.d - -endif # end of if python - -if GUILE - -msdd_rs_scmlib_LTLIBRARIES = \ - libguile-gnuradio-msdd_rs.la -libguile_gnuradio_msdd_rs_la_SOURCES = \ - guile/msdd_rs.cc \ - $(msdd_rs_la_swig_sources) -nobase_msdd_rs_scm_DATA = \ - gnuradio/msdd_rs.scm \ - gnuradio/msdd_rs-primitive.scm -libguile_gnuradio_msdd_rs_la_LIBADD = \ - $(STD_SWIG_LA_LIB_ADD) \ - $(msdd_rs_la_swig_libadd) -libguile_gnuradio_msdd_rs_la_LDFLAGS = \ - $(STD_SWIG_LA_LD_FLAGS) \ - $(msdd_rs_la_swig_ldflags) -libguile_gnuradio_msdd_rs_la_CXXFLAGS = \ - $(STD_SWIG_CXX_FLAGS) \ - -I$(top_builddir) \ - $(msdd_rs_la_swig_cxxflags) - -guile/msdd_rs.cc: gnuradio/msdd_rs.scm -gnuradio/msdd_rs.scm: msdd_rs.i -gnuradio/msdd_rs-primitive.scm: gnuradio/msdd_rs.scm - -# Include the guile dependencies for this file --include guile/msdd_rs.d - -endif # end of GUILE - - diff --git a/gr-msdd6000/src/README b/gr-msdd6000/src/README deleted file mode 100644 index 230b7b6cf..000000000 --- a/gr-msdd6000/src/README +++ /dev/null @@ -1,34 +0,0 @@ -This block implements an interface between the Softronics MSDD6000 and GR - -Jul 13, 2008 - -Tools / Waveforms - - - - python-examples/new_msdd/fft.py - A clone of the original usrp_fft.py - adapted to work with the new msdd.source_simple - source block. - run ./new_msdd_fft.py -W - for waterfall mode. - - -GNU Radio Blocks, - - - msdd.source_simple - this block produces a stream of - interleaved complex shorts and - currently works with FAPP.LDR - - if you want complex floats, - put a gr.interleaved_short_to_complex() - block immidiately following. - - - - msdd.source_s / source_c / source_base - These were written with the - old TCP based app.ldr protocol - and will no longer work. - data was never streamed - without discontinuities - through this method. diff --git a/gr-msdd6000/src/msdd.i b/gr-msdd6000/src/msdd.i deleted file mode 100644 index 935bf2b58..000000000 --- a/gr-msdd6000/src/msdd.i +++ /dev/null @@ -1,64 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2004,2009 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -%include "gnuradio.i" // the common stuff - -%{ -#include "msdd_source_simple.h" -%} - - -GR_SWIG_BLOCK_MAGIC(msdd,source_simple) - -msdd_source_simple_sptr -msdd_make_source_simple ( - const char *src, - unsigned short port_src - ); - -class msdd_source_simple : public gr_sync_block { - protected: - msdd_source_simple( - const char *src, - unsigned short port_src - ); - - public: - ~msdd_source_c(); - int work (int noutput_items, - gr_vector_const_void_star &input_items, - gr_vector_void_star &output_items); - - bool start(); - bool stop(); - - long adc_freq(); - int decim_rate(); - gr_vector_int gain_range(); - gr_vector_float freq_range(); - - bool set_decim_rate(unsigned int); - bool set_rx_freq(int,double); - bool set_pga(int,double); - - - }; diff --git a/gr-msdd6000/src/msdd6000.cc b/gr-msdd6000/src/msdd6000.cc deleted file mode 100644 index f0a13936c..000000000 --- a/gr-msdd6000/src/msdd6000.cc +++ /dev/null @@ -1,209 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008,2009 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifdef HAVE_CONFIG_H -#include <config.h> -#endif -#include <msdd6000.h> - -#include <stdio.h> -#include <string.h> -#include <unistd.h> - -#ifdef HAVE_ARPA_INET_H -#include <arpa/inet.h> -#endif -#ifdef HAVE_NETINET_IN_H -#include <netinet/in.h> -#endif -#ifdef HAVE_SYS_SOCKET_H -#include <sys/socket.h> -#endif - -#define DEBUG(A) printf("=debug=> %s\n", A) - -static void -optimize_socket(int socket); - -/* - * Holds types that need autoconf help. They're here and not in the .h file because - * here we've got access to config.h - */ -class MSDD6000::detail { -public: - struct sockaddr_in d_sockaddr; -}; - - -MSDD6000::MSDD6000(char* addr) - : d_detail(new MSDD6000::detail()) -{ - d_sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP); - - optimize_socket(d_sock); - - - // set up remote sockaddr -// int s = inet_aton(addr, &d_adx); - d_detail->d_sockaddr.sin_family = AF_INET; - d_detail->d_sockaddr.sin_port = htons(10000); - int s = inet_aton(addr, &d_detail->d_sockaddr.sin_addr); - - // set up local sockaddr - struct in_addr d_myadx; - struct sockaddr_in d_mysockaddr; - short int port = 10010; - d_myadx.s_addr = INADDR_ANY; - d_mysockaddr.sin_family = AF_INET; - d_mysockaddr.sin_port = htons(port); - memcpy(&d_mysockaddr.sin_addr.s_addr, &d_myadx.s_addr, sizeof(in_addr)); - //d_sockaddr.sin_addr = INADDR_ANY; - s = bind(d_sock, (const sockaddr*) &d_mysockaddr, sizeof(d_mysockaddr)); - - // set default values - d_decim = 2; - d_ddc_gain = 2; - d_rf_attn = 0; - d_state = STATE_STOPPED; -} - -MSDD6000::~MSDD6000() -{ - // printf("MSDD6000::Destructing\n"); - close(d_sock); -} - - -static void -optimize_socket(int socket){ -#define BANDWIDTH 1000000000/8 -#define DELAY 0.5 - int ret; - - int sock_buf_size = static_cast<int>(2*BANDWIDTH*DELAY); - char textbuf[512]; - snprintf(textbuf, sizeof(textbuf), "%d", sock_buf_size); - printf("sock_buf_size = %d\n", sock_buf_size); - - ret = setsockopt(socket, SOL_SOCKET, SO_SNDBUF, - &sock_buf_size, sizeof(sock_buf_size)); - - ret = setsockopt(socket, SOL_SOCKET, SO_RCVBUF, - &sock_buf_size, sizeof(sock_buf_size)); - - int uid = getuid(); - if(uid!=0){ - printf(" ****** COULD NOT OPTIMIZE SYSTEM NETWORK PARAMETERS BECAUSE YOU ARE NOT RUNNING AS ROOT *******\n ****** YOUR MSDD6000 RECIEVER PERFORMANCE IS GOING TO BE TERRIBLE *******\n"); - return; - } - - - // SET UP SOME SYSTEM WIDE TCP SOCKET PARAMETERS - // FIXME seems like kind of a big hammer. Are you sure you need this? - FILE* fd = fopen("/proc/sys/net/core/netdev_max_backlog", "w"); - if (fd){ - fwrite("10000", 1, strlen("10000"), fd); - fclose(fd); - } - - fd = fopen("/proc/sys/net/core/rmem_max", "w"); - if (fd){ - fwrite(textbuf, 1, strlen(textbuf), fd); - fclose(fd); - } - - fd = fopen("/proc/sys/net/core/wmem_max", "w"); - if (fd){ - fwrite(textbuf, 1, strlen(textbuf), fd); - fclose(fd); - } - - // just incase these were rejected before because of max sizes... - - ret = setsockopt( socket, SOL_SOCKET, SO_SNDBUF, - (char *)&sock_buf_size, sizeof(sock_buf_size) ); - - ret = setsockopt( socket, SOL_SOCKET, SO_RCVBUF, - (char *)&sock_buf_size, sizeof(sock_buf_size) ); - -} - - -void MSDD6000::set_decim(int decim_pow2){ - DEBUG("SETTING NEW DECIM"); - d_decim = decim_pow2; - - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -} - -void MSDD6000::set_rf_attn(int attn){ - DEBUG("SETTING NEW RF ATTN"); - d_rf_attn = attn; - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -} - -void MSDD6000::set_ddc_gain(int gain){ - DEBUG("SETTING NEW DDC GAIN"); - d_ddc_gain = gain; - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -} - -void MSDD6000::set_fc(int center_mhz, int offset_hz){ - DEBUG("SETTING NEW FC"); - d_fc_mhz = center_mhz; - d_offset_hz = offset_hz; - - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -} - - -void MSDD6000::start(){ - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); - d_state = STATE_STARTED; - } - - -void MSDD6000::stop(){ - // new request with 0 decim tells it to halt - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, 0, d_offset_hz); - d_state = STATE_STOPPED; - } - - -void MSDD6000::send_request(float freq_mhz, float rf_attn, float ddc_gain, float ddc_dec, float ddc_offset_hz){ - static char buff[512]; - sprintf(buff, "%f %f %f %f %f\n",freq_mhz, rf_attn, ddc_gain, ddc_dec, ddc_offset_hz); - printf("sending: %s\n", buff); - int flags = 0; - sendto( d_sock, buff, strlen(buff)+1, flags, - (const sockaddr*)&(d_detail->d_sockaddr), sizeof(d_detail->d_sockaddr)); - } - - -int MSDD6000::read(char* buf, int size){ - int flags = 0; - return recv(d_sock, buf, size, flags); - } - - diff --git a/gr-msdd6000/src/msdd6000.h b/gr-msdd6000/src/msdd6000.h deleted file mode 100644 index 808a8386f..000000000 --- a/gr-msdd6000/src/msdd6000.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef MSDD6000_H -#define MSDD6000_H - -#include <boost/scoped_ptr.hpp> - -class MSDD6000 { - class detail; - - //! holds objects with system dependent types - boost::scoped_ptr<detail> d_detail; - -public: - - enum state { - STATE_STOPPED, STATE_STARTED, - }; - - MSDD6000(char* ip_addr); - ~MSDD6000(); - - void set_decim(int decim_pow2); - void set_fc(int center_mhz, int offset_hz); - void set_ddc_gain(int gain); - void set_rf_attn(int attn); - - void set_output(int mode, void* arg); - - void start(); - void stop(); - - void send_request(float,float,float,float,float); - int read(char*, int); - - int d_decim; - int d_fc_mhz; - int d_offset_hz; - int d_rf_attn; - int d_ddc_gain; - int d_sock; - state d_state; - -}; - - -#endif diff --git a/gr-msdd6000/src/msdd6000_rs.cc b/gr-msdd6000/src/msdd6000_rs.cc deleted file mode 100644 index d78f2b4da..000000000 --- a/gr-msdd6000/src/msdd6000_rs.cc +++ /dev/null @@ -1,286 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifdef HAVE_CONFIG_H -#include <config.h> -#endif -#include <msdd6000_rs.h> - -#include <stdio.h> -#include <string.h> -#include <unistd.h> - -#ifdef HAVE_ARPA_INET_H -#include <arpa/inet.h> -#endif -#ifdef HAVE_NETINET_IN_H -#include <netinet/in.h> -#endif -#ifdef HAVE_SYS_SOCKET_H -#include <sys/socket.h> -#endif - -#define DEBUG(A) printf("=debug=> %s\n", A) - -static void -optimize_socket(int socket); - -/* - * Holds types that need autoconf help. They're here and not in the .h file because - * here we've got access to config.h - */ -class MSDD6000_RS::detail { -public: - struct sockaddr_in d_sockaddr; -}; - - -MSDD6000_RS::MSDD6000_RS(char* addr) - : d_detail(new MSDD6000_RS::detail()) -{ - d_sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP); - - optimize_socket(d_sock); - - - // set up remote sockaddr -// int s = inet_aton(addr, &d_adx); - d_detail->d_sockaddr.sin_family = AF_INET; - d_detail->d_sockaddr.sin_port = htons(10000); - int s = inet_aton(addr, &d_detail->d_sockaddr.sin_addr); - - // set up local sockaddr - struct in_addr d_myadx; - struct sockaddr_in d_mysockaddr; - short int port = 10010; - d_myadx.s_addr = INADDR_ANY; - d_mysockaddr.sin_family = AF_INET; - d_mysockaddr.sin_port = htons(port); - memcpy(&d_mysockaddr.sin_addr.s_addr, &d_myadx.s_addr, sizeof(in_addr)); - //d_sockaddr.sin_addr = INADDR_ANY; - s = bind(d_sock, (const sockaddr*) &d_mysockaddr, sizeof(d_mysockaddr)); - - // set default values - //d_decim = 2; - d_ddc_gain = 2; - d_rf_attn = 0; - d_fc_mhz = 3500; - d_offset_hz = 0; - d_ddc_gain = 0; - d_ddc_sample_rate_khz = 25600; - d_ddc_bw_khz = 25600; - d_start = 0; - d_state = STATE_STOPPED; -} - -MSDD6000_RS::~MSDD6000_RS() -{ - //printf("MSDD6000_RS::Destructing\n"); - close(d_sock); -} - - -static void -optimize_socket(int socket){ -#define BANDWIDTH 1000000000/8 -#define DELAY 0.5 - int ret; - - int sock_buf_size = static_cast<int>(2*BANDWIDTH*DELAY); - char textbuf[512]; - snprintf(textbuf, sizeof(textbuf), "%d", sock_buf_size); - printf("sock_buf_size = %d\n", sock_buf_size); - - ret = setsockopt(socket, SOL_SOCKET, SO_SNDBUF, - &sock_buf_size, sizeof(sock_buf_size)); - - ret = setsockopt(socket, SOL_SOCKET, SO_RCVBUF, - &sock_buf_size, sizeof(sock_buf_size)); - - int uid = getuid(); - if(uid!=0){ - printf(" ****** COULD NOT OPTIMIZE SYSTEM NETWORK PARAMETERS BECAUSE YOU ARE NOT RUNNING AS ROOT *******\n ****** YOUR MSDD6000_RS RECIEVER PERFORMANCE IS GOING TO BE TERRIBLE *******\n"); - return; - } - - - // SET UP SOME SYSTEM WIDE TCP SOCKET PARAMETERS - // FIXME seems like kind of a big hammer. Are you sure you need this? - FILE* fd = fopen("/proc/sys/net/core/netdev_max_backlog", "w"); - if (fd){ - fwrite("10000", 1, strlen("10000"), fd); - fclose(fd); - } - - fd = fopen("/proc/sys/net/core/rmem_max", "w"); - if (fd){ - fwrite(textbuf, 1, strlen(textbuf), fd); - fclose(fd); - } - - fd = fopen("/proc/sys/net/core/wmem_max", "w"); - if (fd){ - fwrite(textbuf, 1, strlen(textbuf), fd); - fclose(fd); - } - - // just incase these were rejected before because of max sizes... - - ret = setsockopt( socket, SOL_SOCKET, SO_SNDBUF, - (char *)&sock_buf_size, sizeof(sock_buf_size) ); - - ret = setsockopt( socket, SOL_SOCKET, SO_RCVBUF, - (char *)&sock_buf_size, sizeof(sock_buf_size) ); - -} - - -//void MSDD6000_RS::set_decim(int decim_pow2){ -// DEBUG("SETTING NEW DECIM"); -// d_decim = decim_pow2; -// -// if(d_state==STATE_STARTED) -// send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -//} - -void MSDD6000_RS::set_rf_attn(int attn){ - DEBUG("SETTING NEW RF ATTN"); - d_rf_attn = attn; - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -} - -void MSDD6000_RS::set_ddc_gain(int gain){ - DEBUG("SETTING NEW DDC GAIN"); - d_ddc_gain = gain; - if(d_state==STATE_STARTED) - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -} - -void MSDD6000_RS::set_fc(int center_mhz, int offset_hz){ - DEBUG("SETTING NEW FC"); - d_fc_mhz = center_mhz; - d_offset_hz = offset_hz; - - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -// if(d_state==STATE_STARTED) -// send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_decim, d_offset_hz); -// send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -// -} - -void MSDD6000_RS::set_ddc_samp_rate(float sample_rate_khz){ - DEBUG("SETTING NEW SAMPLE RATE"); - d_ddc_sample_rate_khz = sample_rate_khz; - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -} - -void MSDD6000_RS::set_ddc_bw(float bw_khz){ - DEBUG("SETTING NEW DDC BW"); - d_ddc_bw_khz = bw_khz; - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); -} - -void MSDD6000_RS::start(){ - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); - return; -} - -void MSDD6000_RS::stop(){ - // new request with 0 decim tells it to halt - stop_data(); -} - - -int MSDD6000_RS::start_data(){ - d_start = 1; - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); - d_state = STATE_STARTED; - return 0; - } - - -int MSDD6000_RS::stop_data(){ - // new request with 0 decim tells it to halt - d_start = 0; - send_request(d_fc_mhz, d_rf_attn, d_ddc_gain, d_offset_hz, d_ddc_sample_rate_khz, d_ddc_bw_khz, d_start); - d_state = STATE_STOPPED; - return 0; - } - -/* Query functions */ -float MSDD6000_RS::pull_ddc_samp_rate(){ - return d_ddc_sample_rate_khz; -} -float MSDD6000_RS::pull_ddc_bw(){ - return d_ddc_bw_khz; -} - -float MSDD6000_RS::pull_rx_freq(){ - return d_fc_mhz; -} -int MSDD6000_RS::pull_ddc_gain(){ - return d_ddc_gain; -} - -int MSDD6000_RS::pull_rf_atten(){ - return d_rf_attn; -} - - -void MSDD6000_RS::send_request(float freq_mhz, float rf_attn, float ddc_gain, float ddc_offset_hz, float ddc_samp_rate_khz, float ddc_input_bw_khz, float ddc_start){ - static char buff[512]; - // Send MSDD6000_RS control frame. - sprintf(buff, "%f %f %f %f %f %f %f\n",freq_mhz, rf_attn, ddc_gain, ddc_offset_hz, ddc_samp_rate_khz, ddc_input_bw_khz, ddc_start); //ddc_dec, ddc_offset_hz); - printf("sending: %s\n", buff); - int flags = 0; - sendto( d_sock, buff, strlen(buff)+1, flags, - (const sockaddr*)&(d_detail->d_sockaddr), sizeof(d_detail->d_sockaddr)); - } - - -int MSDD6000_RS::read(char* buf, int size){ - int flags = 0; - return recv(d_sock, buf, size, flags); - } - -int MSDD6000_RS::parse_control(char* buf, int size){ - //packet_len = sprintf(&txbuff[6], "%f %f %f %f %f %f %f",downsamp,ddc_dec_rate,ddc_step_int,ddc_step_frac,ddc_samp_rate_khz,ddc_input_bw_khz,ddc_start); - - float downsamp; - float ddc_dec_rate; - float ddc_step_int; - float ddc_step_frac; - float ddc_samp_rate_khz; - float ddc_input_bw_khz; - float ddc_start; - - sscanf(&buf[6],"%f %f %f %f %f %f %f",&downsamp,&ddc_dec_rate,&ddc_step_int,&ddc_step_frac,&ddc_samp_rate_khz,&ddc_input_bw_khz,&ddc_start); - - // pull off sample rate - d_ddc_sample_rate_khz = ddc_samp_rate_khz; - printf("Sample Rate %f\n",d_ddc_sample_rate_khz); - // pull off bw - d_ddc_bw_khz = ddc_input_bw_khz; - printf("BW %f\n", d_ddc_bw_khz); - return 0; -} - - diff --git a/gr-msdd6000/src/msdd6000_rs.h b/gr-msdd6000/src/msdd6000_rs.h deleted file mode 100644 index 4be4624be..000000000 --- a/gr-msdd6000/src/msdd6000_rs.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef MSDD_RS__RS_6000_H -#define MSDD_RS__RS_6000_H - -#include <boost/scoped_ptr.hpp> - -class MSDD6000_RS { - class detail; - - //! holds objects with system dependent types - boost::scoped_ptr<detail> d_detail; - -public: - - enum state { - STATE_STOPPED, STATE_STARTED - }; - - MSDD6000_RS(char* ip_addr); - ~MSDD6000_RS(); - - /* set functions -- sets digitizer parameters */ - - // void set_output(int mode, void* arg); - - void set_rf_attn(int attn); - void set_ddc_gain(int gain); - void set_fc(int center_mhz, int offset_hz); - void set_ddc_samp_rate(float sample_rate_khz); - void set_ddc_bw(float bw_khz); - - void start(); - void stop(); - - /* function starts the flow of data from the digitizer */ - int start_data(); - /* function stops the flow of data from the digitizer */ - int stop_data(); - - /* query functions -- queries digitizer 'actual' parameters */ - float pull_ddc_samp_rate(); - float pull_ddc_bw(); - float pull_rx_freq(); - int pull_ddc_gain(); - int pull_rf_atten(); - - void send_request(float,float,float,float,float,float,float); - int read(char*, int); - - int parse_control(char*, int); - -private: - // parameters for a receiver object. - int d_fc_mhz; - int d_offset_hz; - int d_rf_attn; - int d_ddc_gain; - float d_ddc_sample_rate_khz; - float d_ddc_bw_khz; - int d_start; - int d_sock; - state d_state; - -}; - - -#endif diff --git a/gr-msdd6000/src/msdd_buffer_copy_behaviors.h b/gr-msdd6000/src/msdd_buffer_copy_behaviors.h deleted file mode 100644 index 398f8ae66..000000000 --- a/gr-msdd6000/src/msdd_buffer_copy_behaviors.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef MSDD_BUFFER_COPY_BEHAVIORS_H_ -#define MSDD_BUFFER_COPY_BEHAVIORS_H_ - -namespace msdd { - - class BufferCopyBehavior - { - public: - virtual void operator() (gr_vector_void_star &a, const void * b, unsigned int output_index, unsigned int nitems) = 0; - virtual ~BufferCopyBehavior() {}; - }; - - template <class Tin, class Tout> - class BufferCopyBehaviorGeneric : public BufferCopyBehavior { - void operator() (gr_vector_void_star &a, const void * b, unsigned int output_index, unsigned int nitems) { - Tout *out(&(reinterpret_cast<Tout *>(a[0]))[output_index]); // sloppy - const Tin *in(reinterpret_cast<const Tin *>(b)); // equisloppy - - for (unsigned int i = 0; i < nitems; ++i) { - out[i] = in[i]; - } - } - }; - - template <class Tin> - class BufferCopyBehaviorComplex : public BufferCopyBehavior { - void operator() (gr_vector_void_star &a, const void * b, unsigned int output_index, unsigned int nitems) { - gr_complex *out(&(reinterpret_cast<gr_complex *>(a[0]))[output_index]); // sloppy - const Tin *in(reinterpret_cast<const Tin *>(b)); // equisloppy - - for (unsigned int i = 0; i < nitems; ++i) { - out[i] = gr_complex (in[4*i+1],in[4*i+3]); - } - } - }; -} - -#endif /*MSDD_BUFFER_COPY_BEHAVIORS_H_*/ diff --git a/gr-msdd6000/src/msdd_rs.i b/gr-msdd6000/src/msdd_rs.i deleted file mode 100644 index 8afb1fb7e..000000000 --- a/gr-msdd6000/src/msdd_rs.i +++ /dev/null @@ -1,103 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2004,2009 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -%include "gnuradio.i" // the common stuff - -%{ -#include "msdd_rs_source_simple.h" -%} - - -GR_SWIG_BLOCK_MAGIC(msdd_rs,source_simple) - -msdd_rs_source_simple_sptr -msdd_rs_make_source_simple ( - const char *src, - unsigned short port_src - ); - -class msdd_rs_source_simple : public gr_sync_block { - protected: - msdd_rs_source_simple( - const char *src, - unsigned short port_src - ); - - public: - ~msdd_rs_source_c(); - int work (int noutput_items, - gr_vector_const_void_star &input_items, - gr_vector_void_star &output_items); - - bool start(); - bool stop(); - - /* function starts the flow of data */ - int start_data(); - - /* function stops the flow of data */ - int stop_data(); - - long pull_adc_freq(); - /* Request the current ddc sample rate */ - float pull_ddc_samp_rate(); - /* Request the current ddc bandwidth */ - float pull_ddc_bw(); - /* Request the current rx freq */ - float pull_rx_freq(); - /* Request current ddc gain */ - int pull_ddc_gain(); - /* Request current RF attenuation */ - int pull_rf_atten(); - - - /* int decim_rate(); */ - gr_vector_int gain_range(); - gr_vector_float freq_range(); - - /* Set Functions */ - /* bool set_decim_rate(unsigned int); */ - bool set_rx_freq(double); /* set_rx_freq(int,double); */ - /* bool set_pga(int,double); */ - - bool set_ddc_gain(double); - /* Set desired sample rate of MSDD6000 -- Note bounds checking is - done by the module and it will return the value actually used in the hardware. */ - bool set_ddc_samp_rate(double); - /* Set desired input BW of MSDD6000 -- Note bounds checking is - // done by the module and it will return the value actually used in the hardware. */ - bool set_ddc_bw(double); - - bool set_rf_atten(double); - - - }; - -#if SWIGGUILE -%scheme %{ -(load-extension-global "libguile-gnuradio-msdd_rs" "scm_init_gnuradio_msdd_rs_module") -%} - -%goops %{ -(use-modules (gnuradio gnuradio_core_runtime)) -%} -#endif diff --git a/gr-msdd6000/src/msdd_rs_source_simple.cc b/gr-msdd6000/src/msdd_rs_source_simple.cc deleted file mode 100644 index 70e692d83..000000000 --- a/gr-msdd6000/src/msdd_rs_source_simple.cc +++ /dev/null @@ -1,240 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008,2010 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifdef HAVE_CONFIG_H -#include <config.h> -#endif - -#include <msdd_rs_source_simple.h> -#include <gr_io_signature.h> -#include <string.h> -#include <cstdio> - - -msdd_rs_source_simple_sptr -msdd_rs_make_source_simple ( const char *src, unsigned short port_src) -{ - return gnuradio::get_initial_sptr(new msdd_rs_source_simple ( src, port_src)); -} - - -msdd_rs_source_simple::msdd_rs_source_simple ( - const char *src, - unsigned short port_src) - : gr_sync_block("MSDD_RS_SOURCE_SIMPLE", - gr_make_io_signature (0,0,0), - gr_make_io_signature (1, 1, sizeof (short))), - rcv(new MSDD6000_RS((char*) src)), d_lastseq(0) -{ -} - -msdd_rs_source_simple::~msdd_rs_source_simple () -{ -} - - -int -msdd_rs_source_simple::work (int noutput_items, - gr_vector_const_void_star &input_items, - gr_vector_void_star &output_items) -{ - -#define BUF_LEN (366*sizeof(short)*2 + 6) - - float* out1 =(float*) output_items[0]; - - char buffer[BUF_LEN]; - /* Read a buffer out -- looking at UDP payload at this point.*/ - rcv->read( &buffer[0], BUF_LEN ); - - //int seq = *((int*) &buffer[2]); - int seq; - memcpy(&seq, &buffer[2], 4*sizeof(char)); - - char type = buffer[0]; - //printf("Sequence %d\n",seq); - - // FIXME get rid of these magic 366's! - if(d_lastseq == -366) - { - if (type != 0){ - /* Received control packet -- parse and update locally stored parameters */ - printf("Parsing control Packet\n"); - rcv->parse_control(&buffer[0], seq); - } - else{ - // not started case - if(seq == 0){ - d_lastseq = 0; - } - else - { - // THROW AWAY SAMPLES WE ARE NOT STARTED YET! - return 0; - } - } - } - // Started case - else - { - if (type != 0){ - /* Received control packet -- parse and update locally stored parameters */ - printf("Parsing control Packet\n"); - rcv->parse_control(&buffer[0], seq); - } - - else { - int samples_missed = seq - d_lastseq - 366; - if(samples_missed > 0) - { - printf("dropped %d samples.\n", samples_missed); - } - d_lastseq = seq; - } - } - - if(noutput_items< 366*2){ - printf("NOT ENOUGH SPACE IN OUTPUT BUFFER!!! >:-(\n"); - } - - memcpy(&out1[0], &buffer[6], BUF_LEN - 6); - -// for(int i = 0; i < 366*2; i++){ -// out1[i] = (float) (*((short*) &buffer[6+2*i]) ); -// } - - return 366*2; -} - -//bool msdd_rs_source_simple::set_decim_rate(unsigned int rate) -//{ -// // FIXME seems buggy. How about a floor or ceil? -// rcv->set_decim((int) log2(rate)); -// return true; -//} - -bool msdd_rs_source_simple::set_rx_freq(double freq) -{ - long new_fc = (long)freq; - rcv->set_fc( new_fc/1000000, new_fc%1000000); - return true; -} - - -bool msdd_rs_source_simple::set_ddc_gain(double gain) -{ - if(gain < 0 || gain > 7){ // only 3 bits available. - printf("GAIN IS OUTSIDE ACCEPTABLE RANGE!\n"); - return false; - } - //decimation gain - rcv->set_ddc_gain((int)gain); - return true; -} - -// Set desired sample rate of MSDD6000 -- Note bounds checking is -// done by the module and it will return the value actually used in the hardware. -bool msdd_rs_source_simple::set_ddc_samp_rate(double rate) -{ - rcv->set_ddc_samp_rate((float) rate); - return true; -} - -// Set desired input BW of MSDD6000 -- Note bounds checking is -// done by the module and it will return the value actually used in the hardware. -bool msdd_rs_source_simple::set_ddc_bw(double bw) -{ - rcv->set_ddc_bw((float) bw); - return true; -} - -bool msdd_rs_source_simple::set_rf_atten(double rf_atten) -{ - rcv->set_rf_attn((int) rf_atten); - return true; -} - -bool msdd_rs_source_simple::start() -{ - rcv->start(); - rcv->stop_data(); - return true; -} - -bool msdd_rs_source_simple::stop() -{ - rcv->stop(); - return true; -} - -int msdd_rs_source_simple::start_data() -{ - return rcv->start_data(); -} - -int msdd_rs_source_simple::stop_data() -{ - return rcv->stop_data(); -} - -/* Query functions */ -long msdd_rs_source_simple::pull_adc_freq(){ - return 102400000; -} - -/* Request the current ddc sample rate */ -float msdd_rs_source_simple::pull_ddc_samp_rate(){ - return(rcv->pull_ddc_samp_rate()); -} - -/* Request the current ddc bandwidth */ -float msdd_rs_source_simple::pull_ddc_bw(){ - return(rcv->pull_ddc_bw()); - -} - -/* Request the current rx freq */ -float msdd_rs_source_simple::pull_rx_freq(){ - return(rcv->pull_rx_freq()); -} - -/* Request current ddc gain */ -int msdd_rs_source_simple::pull_ddc_gain(){ - return(rcv->pull_ddc_gain()); -} - -/* Request current RF attenuation */ -int msdd_rs_source_simple::pull_rf_atten(){ - return(rcv->pull_rf_atten()); -} - -std::vector<int> msdd_rs_source_simple::gain_range(){ - static std::vector<int> r; - r.push_back(0); - r.push_back(12); - return r; -} - -std::vector<float> msdd_rs_source_simple::freq_range(){ - std::vector<float> r; - r.push_back(30.0*1000*1000); - r.push_back(6.0*1000*1000*1000); - return r; -} diff --git a/gr-msdd6000/src/msdd_rs_source_simple.h b/gr-msdd6000/src/msdd_rs_source_simple.h deleted file mode 100644 index f320cbb4d..000000000 --- a/gr-msdd6000/src/msdd_rs_source_simple.h +++ /dev/null @@ -1,87 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifndef INCLUDED_MSDD_RS_SOURCE_SIMPLE_H -#define INCLUDED_MSDD_RS_SOURCE_SIMPLE_H - -#include <gr_sync_block.h> -#include <msdd6000_rs.h> -#include <boost/scoped_ptr.hpp> - -class msdd_rs_source_simple; -typedef boost::shared_ptr<msdd_rs_source_simple> msdd_rs_source_simple_sptr; - - -// public shared_ptr constructor - -msdd_rs_source_simple_sptr msdd_rs_make_source_simple ( const char *src, unsigned short port_src); - - -class msdd_rs_source_simple : public gr_sync_block { - private: - friend msdd_rs_source_simple_sptr - msdd_rs_make_source_simple ( const char *src, unsigned short port_src); - - boost::scoped_ptr<MSDD6000_RS> rcv; - int d_lastseq; - - protected: - msdd_rs_source_simple (const char *src, unsigned short port_src); - - public: - ~msdd_rs_source_simple (); - bool stop(); - bool start(); - - /* function starts the flow of data from the digitizer */ - int start_data(); - /* function stops the flow of data from the digitizer */ - int stop_data(); - - // Do not need this // -// bool set_decim_rate(unsigned int); - /* Adding functions for setting the sample rate and - * receiver bandwidth - */ - - /* hardware commands -- change current state of digitizer */ - bool set_ddc_samp_rate(double); - bool set_ddc_bw(double); - - bool set_rx_freq(double); - bool set_ddc_gain(double); - bool set_rf_atten(double); - - int work(int, gr_vector_const_void_star&, gr_vector_void_star&); - - /* Query methods -- query current state of digitizer */ - long pull_adc_freq(); - float pull_ddc_samp_rate(); - float pull_ddc_bw(); - float pull_rx_freq(); - int pull_ddc_gain(); - int pull_rf_atten(); - - /* Pulling back gain and frequency ranges */ - std::vector<int> gain_range(); - std::vector<float> freq_range(); -}; - -#endif /* INCLUDED_MSDD_RS__RS__SOURCE_C_H */ diff --git a/gr-msdd6000/src/msdd_source_simple.cc b/gr-msdd6000/src/msdd_source_simple.cc deleted file mode 100644 index 20b15c43d..000000000 --- a/gr-msdd6000/src/msdd_source_simple.cc +++ /dev/null @@ -1,168 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008,2009,2010 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifdef HAVE_CONFIG_H -#include <config.h> -#endif - -#include <msdd_source_simple.h> -#include <gr_io_signature.h> -#include <string.h> -#include <cstdio> - - -msdd_source_simple_sptr -msdd_make_source_simple (const char *src, unsigned short port_src) -{ - return gnuradio::get_initial_sptr(new msdd_source_simple ( src, port_src)); -} - - -msdd_source_simple::msdd_source_simple (const char *src, - unsigned short port_src) - : gr_sync_block("MSDD_SOURCE_SIMPLE", - gr_make_io_signature (0,0,0), - gr_make_io_signature (1, 1, sizeof (short))), - rcv(new MSDD6000((char*) src)), d_lastseq(0), d_firstrun(true) -{ - set_output_multiple(MSDD_COMPLEX_SAMPLES_PER_PACKET*2); -} - -msdd_source_simple::~msdd_source_simple () -{ -} - - -int -msdd_source_simple::work (int noutput_items, - gr_vector_const_void_star &input_items, - gr_vector_void_star &output_items) -{ - -#define BUF_LEN (MSDD_COMPLEX_SAMPLES_PER_PACKET*sizeof(short)*2 + 6) - - signed short* out1 =(signed short*) output_items[0]; - - for(int i=0; i<floor(noutput_items*1.0/(2*MSDD_COMPLEX_SAMPLES_PER_PACKET));i++){ - char buffer[BUF_LEN]; - rcv->read( &buffer[0], BUF_LEN ); - - //int seq = *((int*) &buffer[2]); - int seq; - memcpy(&seq, &buffer[2], 4*sizeof(char)); - - if(d_lastseq == -MSDD_COMPLEX_SAMPLES_PER_PACKET){ - // not started case - if(seq == 0){ - d_lastseq = 0; - } else { - // THROW AWAY SAMPLES WE ARE NOT STARTED YET! - return 0; - } - - } else { - // started case - int samples_missed = seq - d_lastseq - MSDD_COMPLEX_SAMPLES_PER_PACKET; - if(samples_missed > 0){ - if(d_firstrun == true){ - // we may have missed some initial samples off the beginning of - // a stream but there are no drop outs in the middle of what we have - } else { - printf("dropped %d samples.\n", samples_missed); - } - } - d_lastseq = seq; - } - - int out_idx = i*MSDD_COMPLEX_SAMPLES_PER_PACKET*2; - memcpy(&out1[out_idx], &buffer[6], BUF_LEN - 6); - d_firstrun = false; - } - - return noutput_items; - -} - -bool msdd_source_simple::set_decim_rate(unsigned int rate) -{ - rcv->set_decim((int) floor(log2(rate))); - return true; -} - - -bool msdd_source_simple::set_rx_freq(int channel, double freq) -{ - long new_fc = (long)freq; - rcv->set_fc( new_fc/1000000, new_fc%1000000); - return true; -} - - -bool msdd_source_simple::set_pga(int which, double gain) -{ - if(gain < 0 || gain > 10){ - printf("GAIN IS OUTSIDE ACCEPTABLE RANGE!\n"); - return false; - } - // ok i lied this is not really a pga, its decimation gain - rcv->set_ddc_gain((int)gain); - return true; -} - - -bool msdd_source_simple::start() -{ - rcv->start(); - return true; -} - - -bool msdd_source_simple::stop() -{ - rcv->stop(); - return true; -} - -long msdd_source_simple::adc_freq() -{ - return 102400000; -} - -int msdd_source_simple::decim_rate() -{ - return 1 << rcv->d_decim; -} - - -std::vector<int> msdd_source_simple::gain_range() -{ - static std::vector<int> r; - r.push_back(0); - r.push_back(12); - return r; -} - -std::vector<float> msdd_source_simple::freq_range() -{ - std::vector<float> r; - r.push_back(30.0*1000*1000); - r.push_back(6.0*1000*1000*1000); - return r; -} diff --git a/gr-msdd6000/src/msdd_source_simple.h b/gr-msdd6000/src/msdd_source_simple.h deleted file mode 100644 index 142c544a4..000000000 --- a/gr-msdd6000/src/msdd_source_simple.h +++ /dev/null @@ -1,68 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2008 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifndef INCLUDED_MSDD_SOURCE_SIMPLE_H -#define INCLUDED_MSDD_SOURCE_SIMPLE_H - -#include <gr_sync_block.h> -#include <msdd6000.h> -#include <boost/scoped_ptr.hpp> - -#define MSDD_COMPLEX_SAMPLES_PER_PACKET 366 - -class msdd_source_simple; -typedef boost::shared_ptr<msdd_source_simple> msdd_source_simple_sptr; - - -// public shared_ptr constructor - -msdd_source_simple_sptr msdd_make_source_simple(const char *src, unsigned short port_src); - - -class msdd_source_simple : public gr_sync_block { - private: - friend msdd_source_simple_sptr - msdd_make_source_simple(const char *src, unsigned short port_src); - - boost::scoped_ptr<MSDD6000> rcv; - int d_lastseq; - bool d_firstrun; - - protected: - msdd_source_simple(const char *src, unsigned short port_src); - - public: - ~msdd_source_simple(); - bool stop(); - bool start(); - - bool set_decim_rate(unsigned int); - bool set_rx_freq(int,double); - bool set_pga(int,double); - - int work(int, gr_vector_const_void_star&, gr_vector_void_star&); - - long adc_freq(); - int decim_rate(); - std::vector<int> gain_range(); - std::vector<float> freq_range(); -}; - -#endif /* INCLUDED_MSDD_SOURCE_C_H */ diff --git a/gr-msdd6000/src/python-examples/msdd_dynamics.py b/gr-msdd6000/src/python-examples/msdd_dynamics.py deleted file mode 100755 index 8cd1e52bc..000000000 --- a/gr-msdd6000/src/python-examples/msdd_dynamics.py +++ /dev/null @@ -1,99 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr -from gnuradio import msdd -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import time - -class benchmark_msdd6000(gr.top_block): - def __init__(self, address, options): - gr.top_block.__init__(self) - - # Extract the initial options - self.frequency = options.frequency - self.filename = options.filename - self.decim = options.decim - self.gain = options.gain - self.address = address - - # Set up and initialize the MSDD receiver - self.port = 10001 # required port - self.src = msdd.source_c(0, 1, self.address, self.port) - self.src.set_decim_rate(self.decim) - self.src.set_desired_packet_size(0, 1460) - self.src.set_pga(0, self.gain) - self.src.set_rx_freq(0, self.frequency) - - # Display some info - print "Min PGA: ", self.src.pga_min() - print "Max PGA: ", self.src.pga_max() - print "PGA: ", self.src.pga(0) - print "Decim: ", self.src.decim_rate() - print "Freq: ", self.src.rx_freq(0) - - # Build a file sink to save the info for post analysis - self.snk = gr.file_sink(gr.sizeof_gr_complex, self.filename) - - # Connect the reciever source to file sink - self.connect(self.src, self.snk) - -def main(): - ''' This is a simple little script to play with retunning of the MSDD board. - You can cycle through frequencies or the attenuation of the board here. - ''' - - usage="%prog: [options] host_address" - parser = OptionParser(usage=usage, option_class=eng_option, conflict_handler="resolve") - parser.add_option("-f", "--frequency", type="eng_float", default=100e6, - help="set frequency (Hz) [default=%default]") - parser.add_option("-d", "--decim", type="int", default=256, - help="set decimation rate [default=%default]") - parser.add_option("-g", "--gain", type="int", default=32, - help="set receiver gain (dB) [default=%default]") - parser.add_option("-F", "--filename", type="string", default="output.dat", - help="set output filename [default=%default]") - (options, args) = parser.parse_args () - host_address = args[0] - - # Set up benchmark system that simply connects the MSDD source to a file sink - tb = benchmark_msdd6000(host_address, options) - tb.start() # start it here - - # Adjust your parameters here. Use the time.sleep(x) function to set a wait period - # between adjusting the parameter. - for i in range(7): - time.sleep(0.5) - if 0: - freq = (tb.src.rx_freq(0) + 1) * 1e6 - tb.src.set_rx_freq(0, freq) - print "Setting frequency: ", freq - if 1: - pga = tb.src.pga(0)+10 - tb.src.set_pga(0, pga) - print "Setting PGA: ", pga - - tb.stop() # stop the radio - -if __name__ == '__main__': - main() diff --git a/gr-msdd6000/src/python-examples/msdd_fft.py b/gr-msdd6000/src/python-examples/msdd_fft.py deleted file mode 100755 index 813a77d38..000000000 --- a/gr-msdd6000/src/python-examples/msdd_fft.py +++ /dev/null @@ -1,277 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2004,2005,2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import msdd -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2, form, slider -from optparse import OptionParser -import wx -import sys - - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem - return (0, 0) - if u.db[1][0].dbid() >= 0: - return (1, 0) - return (0, 0) - - -class app_top_block(stdgui2.std_top_block): - def __init__(self, frame, panel, vbox, argv): - stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv) - - self.frame = frame - self.panel = panel - - parser = OptionParser(option_class=eng_option) - parser.add_option("-w", "--which", type="int", default=0, - help="select which MSDD (0, 1, ...) default is %default", - metavar="NUM") - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="select MSDD Rx side A or B (default=first one with a daughterboard)") - parser.add_option("-A", "--antenna", default=None, - help="select Rx Antenna (only on RFX-series boards)") - parser.add_option("-d", "--decim", type="int", default=16, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=None, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-W", "--waterfall", action="store_true", default=False, - help="Enable waterfall display") - parser.add_option("-8", "--width-8", action="store_true", default=False, - help="Enable 8-bit samples across USB") - parser.add_option("-S", "--oscilloscope", action="store_true", default=False, - help="Enable oscilloscope display") - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - - self.show_debug_info = True - - # build the graph - - #self.u = MSDD.source_simo(which=options.which, decim_rate=options.decim) - self.u = msdd.source_simple("192.168.1.200", 0) - self.u.set_decim_rate(options.decim) #(16) - -# msdd_src = gr.file_source(gr.sizeof_gr_complex, 'msdd.dat') -# thr = gr.throttle(gr.sizeof_gr_complex, 200000) -# self.connect(msdd_src, thr) - -# if options.rx_subdev_spec is None: -# options.rx_subdev_spec = pick_subdevice(self.u) -# self.u.set_mux(MSDD.determine_rx_mux_value(self.u, options.rx_subdev_spec)) - -# if options.width_8: -# width = 8 -# shift = 8 -# format = self.u.make_format(width, shift) -# print "format =", hex(format) -# r = self.u.set_format(format) -# print "set_format =", r - - # determine the daughterboard subdevice we're using -# self.subdev = MSDD.selected_subdev(self.u, options.rx_subdev_spec) - -# print "Initial Freq", self.u.rx_freq(0), "deci: ", self.u.decim_rate() -# input_rate = 50e6 / self.u.decim_rate() - input_rate = 50e6 / options.decim; - - if options.waterfall: - self.scope = \ - waterfallsink2.waterfall_sink_c (panel, fft_size=1024, sample_rate=input_rate) - elif options.oscilloscope: - self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate) - else: - self.scope = fftsink2.fft_sink_c (panel, fft_size=1024, sample_rate=input_rate) - -# self.connect(self.u, self.scope) - - msdd_sink = gr.file_sink(gr.sizeof_gr_complex, 'schmen1.dat') - - self.conv = gr.interleaved_short_to_complex(); - self.connect(self.u, self.conv, msdd_sink) - self._build_gui(vbox) - - # set initial values - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - #g = self.subdev.gain_range() - self.gain_range = (20,70,.5); - options.gain = float(self.gain_range[0]+self.gain_range[1])/2 - - if options.freq is None: - # if no freq was specified, use the mid-point - #r = self.subdev.freq_range() - r = (30e6,6e9,1e6) - options.freq = float(r[0]+r[1])/2 - - self.set_gain(options.gain) -# -# if options.antenna is not None: -# print "Selecting antenna %s" % (options.antenna,) -# self.subdev.select_rx_antenna(options.antenna) - - if self.show_debug_info: - #self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['decim'].set_value(options.decim) - # self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - # self.myform['dbname'].set_value(self.subdev.name()) - self.myform['baseband'].set_value(0) - self.myform['ddc'].set_value(0) - - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - - def _set_status_msg(self, msg): - self.frame.GetStatusBar().SetStatusText(msg, 0) - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - vbox.Add(self.scope.win, 10, wx.EXPAND) - - # add control area at the bottom - self.myform = myform = form.form() - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0, 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Center freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0, 0) - g = self.gain_range = (20,50,.5); - myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, - min=int(g[0]), max=int(g[1]), - callback=self.set_gain) - - hbox.Add((5,0), 0, 0) - vbox.Add(hbox, 0, wx.EXPAND) - - self._build_subpanel(vbox) - - def _build_subpanel(self, vbox_arg): - # build a secondary information panel (sometimes hidden) - - # FIXME figure out how to have this be a subpanel that is always - # created, but has its visibility controlled by foo.Show(True/False) - - def _form_set_decim(kv): - return self.set_decim(kv['decim']) - - if not(self.show_debug_info): - return - - panel = self.panel - vbox = vbox_arg - myform = self.myform - - #panel = wx.Panel(self.panel, -1) - #vbox = wx.BoxSizer(wx.VERTICAL) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - - myform['decim'] = form.int_field( - parent=panel, sizer=hbox, label="Decim", - callback=myform.check_input_and_call(_form_set_decim, self._set_status_msg)) - -# hbox.Add((5,0), 1) -# myform['fs@usb'] = form.static_float_field( -# parent=panel, sizer=hbox, label="Fs@USB") - - hbox.Add((5,0), 1) - myform['dbname'] = form.static_text_field( - parent=panel, sizer=hbox) - - hbox.Add((5,0), 1) - myform['baseband'] = form.static_float_field( - parent=panel, sizer=hbox, label="Analog BB") - - hbox.Add((5,0), 1) - myform['ddc'] = form.static_float_field( - parent=panel, sizer=hbox, label="DDC") - - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - r = self.u.set_rx_freq (0, target_freq) - #r = self.u.tune(0, self.subdev, target_freq) - if r: - self.myform['freq'].set_value(target_freq) # update displayed value -# if self.show_debug_info: -# self.myform['baseband'].set_value(r.baseband_freq) -# self.myform['ddc'].set_value(r.dxc_freq) - return True - - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - #self.subdev.set_gain(gain) - self.u.set_pga(0, gain) - - def set_decim(self, decim): - ok = self.u.set_decim_rate(decim) - if not ok: - print "set_decim failed" - #input_rate = 20e6 / self.u.decim_rate() - #self.scope.set_sample_rate(input_rate) - if self.show_debug_info: # update displayed values - self.myform['decim'].set_value(decim) - #self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - return ok - -def main (): - app = stdgui2.stdapp(app_top_block, "MSDD FFT", nstatus=1) - app.MainLoop() - -if __name__ == '__main__': - main () diff --git a/gr-msdd6000/src/python-examples/msdd_rcv.py b/gr-msdd6000/src/python-examples/msdd_rcv.py deleted file mode 100755 index cc2f3e4a3..000000000 --- a/gr-msdd6000/src/python-examples/msdd_rcv.py +++ /dev/null @@ -1,287 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2005,2006,2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru, eng_notation -from gnuradio import msdd -from gnuradio import blks2 -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import slider, powermate -from gnuradio.wxgui import stdgui2, form -from gnuradio.wxgui import fftsink2 -from optparse import OptionParser -#from usrpm import usrp_dbid -import sys -import math -import wx - -class wfm_rx_block (stdgui2.std_top_block): - def __init__(self,frame,panel,vbox,argv): - stdgui2.std_top_block.__init__ (self,frame,panel,vbox,argv) - - parser=OptionParser(option_class=eng_option) -# parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, -# help="select MSDD Rx side A or B (default=A)") - parser.add_option("-f", "--freq", type="eng_float", default=100.1e6, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=40, - help="set gain in dB (default is midpoint)") -# parser.add_option("-V", "--volume", type="eng_float", default=None, -# help="set volume (default is midpoint)") -# parser.add_option("-O", "--audio-output", type="string", default="", -# help="pcm device name. E.g., hw:0,0 or surround51 or /dev/dsp") - - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - - self.frame = frame - self.panel = panel - - self.vol = 0 - self.gain_range = (10, 70, .5) - self.state = "FREQ" - self.freq = 0 - msdd_decim = 2 - - # build graph - self.fft_size = 8192 - self.sample_rate = 200 - self.u = msdd.source_c(0, 1, "10.45.4.44", 10000) - self.u.set_decim_rate(4) - self.u.set_desired_packet_size(0, 1460*100) - - - #self.u.set_decim_rate(msdd_decim) -# usrp_rate = adc_rate / msdd_decim # 320 kS/s -# chanfilt_decim = 1 -# demod_rate = usrp_rate / chanfilt_decim -# audio_decimation = 10 -# audio_rate = demod_rate / audio_decimation # 32 kHz -# -# if options.rx_subdev_spec is None: -# options.rx_subdev_spec = pick_subdevice(self.u) -# -# self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) -# self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) -# print "Using RX d'board %s" % (self.subdev.side_and_name(),) -# -# -# chan_filt_coeffs = optfir.low_pass (1, # gain -# usrp_rate, # sampling rate -# 80e3, # passband cutoff -# 115e3, # stopband cutoff -# 0.1, # passband ripple -# 60) # stopband attenuation -# #print len(chan_filt_coeffs) -# chan_filt = gr.fir_filter_ccf (chanfilt_decim, chan_filt_coeffs) -# -# self.guts = blks2.wfm_rcv (demod_rate, audio_decimation) -# -# self.volume_control = gr.multiply_const_ff(self.vol) -# -# # sound card as final sink -# audio_sink = audio.sink (int (audio_rate), -# options.audio_output, -# False) # ok_to_block - - # now wire it all together - #self.connect (self.u, chan_filt, self.guts, self.volume_control, audio_sink) - - self._build_gui(vbox) - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - #g = self.subdev.gain_range() - g = self.gain_range - options.gain = float(g[0]+g[1])/2 -# -# if options.volume is None: -# g = self.volume_range() -# options.volume = float(g[0]+g[1])/2 -# -# if abs(options.freq) < 1e6: -# options.freq *= 1e6 - - # set initial values -# - self.set_gain(options.gain) -# self.set_vol(options.volume) - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - print "Frequency: ", self.u.rx_freq(0) - - - def _set_status_msg(self, msg, which=0): - self.frame.GetStatusBar().SetStatusText(msg, which) - - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - self.src_fft = None - if 1: - self.src_fft = fftsink2.fft_sink_c(self.panel, title="Data from MSDD", - fft_size=512, sample_rate=512) -# self.s2f1 = gr.short_to_float() -# self.scope = scopesink2.scope_sink_f(self.panel, sample_rate=self.sample_rate*self.fft_size) - - self.connect (self.u, self.src_fft) - #self.connect (self.s2f1, self.scope) - vbox.Add (self.src_fft.win, 4, wx.EXPAND) -# -# if 1: -# post_filt_fft = fftsink2.fft_sink_f(self.panel, title="Post Demod", -# fft_size=1024, sample_rate=usrp_rate, -# y_per_div=10, ref_level=0) -# self.connect (self.guts.fm_demod, post_filt_fft) -# vbox.Add (post_filt_fft.win, 4, wx.EXPAND) -# -# if 0: -# post_deemph_fft = fftsink2.fft_sink_f(self.panel, title="Post Deemph", -# fft_size=512, sample_rate=audio_rate, -# y_per_div=10, ref_level=-20) -# self.connect (self.guts.deemph, post_deemph_fft) -# vbox.Add (post_deemph_fft.win, 4, wx.EXPAND) - - - # control area form at bottom - self.myform = myform = form.form() - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0) - myform['freq_slider'] = \ - form.quantized_slider_field(parent=self.panel, sizer=hbox, weight=3, - range=(30e6, 6e9, 1e6), - callback=self.set_freq) - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) -# -# myform['volume'] = \ -# form.quantized_slider_field(parent=self.panel, sizer=hbox, label="Volume", -# weight=3, range=self.volume_range(), -# callback=self.set_vol) -# hbox.Add((5,0), 1) - - myform['gain'] = \ - form.quantized_slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, range=self.gain_range, - callback=self.set_gain) - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) -# -# try: -# self.knob = powermate.powermate(self.frame) -# self.rot = 0 -# powermate.EVT_POWERMATE_ROTATE (self.frame, self.on_rotate) -# powermate.EVT_POWERMATE_BUTTON (self.frame, self.on_button) -# except: -# print "FYI: No Powermate or Contour Knob found" - - - def on_rotate (self, event): - self.rot += event.delta - if (self.state == "FREQ"): - if self.rot >= 3: - self.set_freq(self.freq + .1e6) - self.rot -= 3 - elif self.rot <=-3: - self.set_freq(self.freq - .1e6) - self.rot += 3 - else: - step = self.volume_range()[2] - if self.rot >= 3: - self.set_vol(self.vol + step) - self.rot -= 3 - elif self.rot <=-3: - self.set_vol(self.vol - step) - self.rot += 3 - - def on_button (self, event): - if event.value == 0: # button up - return - self.rot = 0 - if self.state == "FREQ": - self.state = "VOL" - else: - self.state = "FREQ" - self.update_status_bar () -# -# -# def set_vol (self, vol): -# g = self.volume_range() -# self.vol = max(g[0], min(g[1], vol)) -# self.volume_control.set_k(10**(self.vol/10)) -# self.myform['volume'].set_value(self.vol) -# self.update_status_bar () - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - r = self.u.set_rx_freq(0, target_freq); - - if r: - self.freq = target_freq - self.myform['freq'].set_value(target_freq) # update displayed value - self.myform['freq_slider'].set_value(target_freq) # update displayed value - self.update_status_bar() - self._set_status_msg("OK", 0) - return True - - self._set_status_msg("Failed", 0) - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - self.u.set_pga(0,gain) - - def update_status_bar (self): - msg = "Volume:%r Setting:%s" % (self.vol, self.state) - self._set_status_msg(msg, 1) - #self.src_fft.set_baseband_freq(self.freq) -# -# def volume_range(self): -# return (-20.0, 0.0, 0.5) - - -if __name__ == '__main__': - app = stdgui2.stdapp (wfm_rx_block, "MSDD FFT RX") - app.MainLoop () diff --git a/gr-msdd6000/src/python-examples/msdd_rs_spec_an.py b/gr-msdd6000/src/python-examples/msdd_rs_spec_an.py deleted file mode 100755 index 4855375b8..000000000 --- a/gr-msdd6000/src/python-examples/msdd_rs_spec_an.py +++ /dev/null @@ -1,350 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr -from gnuradio import msdd_rs -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.qtgui import qtgui -from optparse import OptionParser -import sys,time - -try: - from gnuradio.qtgui import qtgui - from PyQt4 import QtGui, QtCore - import sip -except ImportError: - print "Please install gr-qtgui." - sys.exit(1) - -try: - from msdd_display_qtgui import Ui_MainWindow -except ImportError: - print "Error: could not find msdd_display_qtgui.py:" - print "\t\"pyuic4 msdd_display_qtgui.ui -o msdd_display_qtgui.py\"" - sys.exit(1) - - -# //////////////////////////////////////////////////////////////////// -# Define the QT Interface and Control Dialog -# //////////////////////////////////////////////////////////////////// - - -class main_window(QtGui.QMainWindow): - def __init__(self, snk, fg, parent=None): - - QtGui.QWidget.__init__(self, parent) - self.gui = Ui_MainWindow() - self.gui.setupUi(self) - - self.fg = fg - - # Add the qtsnk widgets to the layout box - self.gui.sinkLayout.addWidget(snk) - - self.gui.dcGainEdit.setText(QtCore.QString("%1").arg(0.001)) - - # Connect up some signals - self.connect(self.gui.pauseButton, QtCore.SIGNAL("clicked()"), - self.pauseFg) - self.connect(self.gui.frequencyEdit, QtCore.SIGNAL("editingFinished()"), - self.frequencyEditText) - self.connect(self.gui.gainEdit, QtCore.SIGNAL("editingFinished()"), - self.gainEditText) - self.connect(self.gui.bandwidthEdit, QtCore.SIGNAL("editingFinished()"), - self.bandwidthEditText) - self.connect(self.gui.amplifierEdit, QtCore.SIGNAL("editingFinished()"), - self.amplifierEditText) - - self.connect(self.gui.actionSaveData, QtCore.SIGNAL("activated()"), - self.saveData) - self.gui.actionSaveData.setShortcut(QtGui.QKeySequence.Save) - - self.connect(self.gui.dcGainEdit, QtCore.SIGNAL("editingFinished()"), - self.dcGainEditText) - self.connect(self.gui.dcCancelCheckBox, QtCore.SIGNAL("clicked(bool)"), - self.dcCancelClicked) - - def pauseFg(self): - if(self.gui.pauseButton.text() == "Pause"): - self.fg.stop() - self.fg.wait() - self.fg.stop_data() - self.gui.pauseButton.setText("Unpause") - else: - self.fg.start() - self.fg.start_data() - self.gui.pauseButton.setText("Pause") - - - # Functions to set the values in the GUI - def set_frequency(self, freq): - self.freq = freq - sfreq = eng_notation.num_to_str(self.freq) - self.gui.frequencyEdit.setText(QtCore.QString("%1").arg(sfreq)) - - def set_gain(self, gain): - self.gain = gain - self.gui.gainEdit.setText(QtCore.QString("%1").arg(self.gain)) - - def set_bandwidth(self, bw): - self.bw = bw - sbw = eng_notation.num_to_str(self.bw) - self.gui.bandwidthEdit.setText(QtCore.QString("%1").arg(sbw)) - - def set_amplifier(self, amp): - self.amp = amp - self.gui.amplifierEdit.setText(QtCore.QString("%1").arg(self.amp)) - - - # Functions called when signals are triggered in the GUI - def frequencyEditText(self): - try: - freq = eng_notation.str_to_num(self.gui.frequencyEdit.text().toAscii()) - self.fg.set_frequency(freq) - self.freq = freq - except RuntimeError: - pass - - def gainEditText(self): - try: - gain = float(self.gui.gainEdit.text()) - self.fg.set_gain(gain) - self.gain = gain - except ValueError: - pass - - def bandwidthEditText(self): - try: - bw = eng_notation.str_to_num(self.gui.bandwidthEdit.text().toAscii()) - self.fg.set_bandwidth(bw) - self.bw = bw - except ValueError: - pass - - def amplifierEditText(self): - try: - amp = float(self.gui.amplifierEdit.text()) - self.fg.set_amplifier_gain(amp) - self.amp = amp - except ValueError: - pass - - def saveData(self): - fileName = QtGui.QFileDialog.getSaveFileName(self, "Save data to file", "."); - if(len(fileName)): - self.fg.save_to_file(str(fileName)) - - def dcGainEditText(self): - gain = float(self.gui.dcGainEdit.text()) - self.fg.set_dc_gain(gain) - - def dcCancelClicked(self, state): - self.dcGainEditText() - self.fg.cancel_dc(state) - - - -class my_top_block(gr.top_block): - def __init__(self): - gr.top_block.__init__(self) - - parser = OptionParser(option_class=eng_option) - parser.add_option("-e", "--interface", type="string", default="eth0", - help="select Ethernet interface, default is eth0") - parser.add_option("-m", "--mac-addr", type="string", default="", - help="select USRP by MAC address, default is auto-select") - parser.add_option("-W", "--bw", type="float", default=1e6, - help="set bandwidth of receiver [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default="2.4G", - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("--fft-size", type="int", default=2048, - help="Set number of FFT bins [default=%default]") - (options, args) = parser.parse_args() - - if len(args) != 0: - parser.print_help() - sys.exit(1) - self.options = options - self.show_debug_info = True - - self.qapp = QtGui.QApplication(sys.argv) - -# self.u = usrp2.source_32fc(options.interface, options.mac_addr) - self.u = msdd_rs.source_simple("192.168.1.20", 10000); - self.conv = gr.interleaved_short_to_complex(); - self._adc_rate = self.u.pull_adc_freq() - self.set_bandwidth(options.bw) - - if options.gain is None: - # if no gain was specified, use the mid-point in dB -# g = self.u.gain_range() - g = [0, 10] - #options.gain = float(g[0]+g[1])/2 - options.gain = float(0) - self.set_gain(options.gain) - - if options.freq is None: - options.freq = 2.4e9; -# # if no frequency was specified, use the mid-point of the subdev -# f = self.u.freq_range() -# options.freq = float(f[0]+f[1])/2 - - self.set_frequency(options.freq) - - self._fftsize = options.fft_size - - - self._freq = options.freq; - self._bandwidth = 400; - - self.set_bandwidth(self._bandwidth); - - self.snk = qtgui.sink_c(options.fft_size, gr.firdes.WIN_BLACKMAN_hARRIS, - self._freq, self._bandwidth, - "USRP2 Display", - True, True, False, True, False) - - # Set up internal amplifier - self.amp = gr.multiply_const_cc(0.0) - self.set_amplifier_gain(0.01) - - # Create a single-pole IIR filter to remove DC - # but don't connect it yet - self.dc_gain = 0.001 - self.dc = gr.single_pole_iir_filter_cc(self.dc_gain) - self.dc_sub = gr.sub_cc() - - self.agc = gr.agc2_cc(1e-3, 1e-5, 0.01, 0.01, 10); - - self.connect(self.u, self.conv, self.snk) - #self.connect(self.u, self.conv, self.amp, self.snk) - - if self.show_debug_info: - print "Decimation rate: ", self._decim - print "Bandwidth: ", self._bandwidth -# print "D'board: ", self.u.daughterboard_id() - - # Get the reference pointer to the SpectrumDisplayForm QWidget - # Wrap the pointer as a PyQt SIP object - # This can now be manipulated as a PyQt4.QtGui.QWidget - self.pysink = sip.wrapinstance(self.snk.pyqwidget(), QtGui.QWidget) - - self.main_win = main_window(self.pysink, self) - - self.main_win.set_frequency(self._freq) - self.main_win.set_gain(self._gain) - self.main_win.set_bandwidth(self._bandwidth) - self.main_win.set_amplifier(self._amp_value) - - self.main_win.show() - - - def save_to_file(self, name): - self.lock() - - # Add file sink to save data - self.file_sink = gr.file_sink(gr.sizeof_gr_complex, name) - self.connect(self.conv, self.file_sink) - - self.unlock() - - def set_gain(self, gain): - self._gain = gain - self.u.set_ddc_gain(self._gain) - - def set_frequency(self, freq): - self._freq = freq - r = self.u.set_rx_freq(freq) - - try: - self.snk.set_frequency_range(self._freq, self._bandwidth) - except: - pass - - def set_bandwidth(self, bw): - self._bandwidth = bw - self._decim = int(self._adc_rate / self._bandwidth) -# self.u.set_decim_rate(self._decim) - r1 = self.u.set_ddc_samp_rate( bw ); - r2 = self.u.set_ddc_bw( bw ); - self.u.start_data(); - - print r1 - print r2; - - time.sleep(0.05); - bw = self.u.pull_ddc_bw(); - sr = self.u.pull_ddc_samp_rate(); - fc = self.u.pull_rx_freq(); - - #self.snk.d_bandwidth = sr; - - print bw; - print sr; - print fc; - -# sys.exit(-1); - - try: - self.snk.set_frequency_range(self._freq, self._bandwidth) - except: - pass - - def set_amplifier_gain(self, amp): - self._amp_value = amp - self.amp.set_k(self._amp_value) - - def set_dc_gain(self, gain): - self.dc.set_taps(gain) - - def cancel_dc(self, state): - self.lock() - - if(state): - self.disconnect(self.u, self.amp) - self.connect(self.u, (self.dc_sub,0)) - self.connect(self.u, self.dc, (self.dc_sub,1)) - self.connect(self.dc_sub, self.amp) - else: - self.disconnect(self.dc_sub, self.amp) - self.disconnect(self.dc, (self.dc_sub,1)) - self.disconnect(self.u, self.dc) - self.disconnect(self.u, (self.dc_sub,0)) - self.connect(self.u, self.amp) - - self.unlock() - -def main (): - tb = my_top_block() - tb.start() - tb.u.start_data(); - tb.snk.exec_(); - -if __name__ == '__main__': - try: - main () - except KeyboardInterrupt: - pass - diff --git a/gr-msdd6000/src/python-examples/msdd_spectrum_sense.py b/gr-msdd6000/src/python-examples/msdd_spectrum_sense.py deleted file mode 100755 index e3d182b03..000000000 --- a/gr-msdd6000/src/python-examples/msdd_spectrum_sense.py +++ /dev/null @@ -1,296 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru, eng_notation, optfir, window -from gnuradio import msdd -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import sys -import math -import struct -from pylab import * -from numpy import array -import time - -matplotlib.interactive(True) -matplotlib.use('TkAgg') - -class tune(gr.feval_dd): - """ - This class allows C++ code to callback into python. - """ - def __init__(self, tb): - gr.feval_dd.__init__(self) - self.tb = tb - - def eval(self, ignore): - """ - This method is called from gr.bin_statistics_f when it wants to change - the center frequency. This method tunes the front end to the new center - frequency, and returns the new frequency as its result. - """ - try: - # We use this try block so that if something goes wrong from here - # down, at least we'll have a prayer of knowing what went wrong. - # Without this, you get a very mysterious: - # - # terminate called after throwing an instance of 'Swig::DirectorMethodException' - # Aborted - # - # message on stderr. Not exactly helpful ;) - - new_freq = self.tb.set_next_freq() - return new_freq - - except Exception, e: - print "tune: Exception: ", e - - -class parse_msg(object): - def __init__(self, sample_rate, percent, alpha=0.01): - self.axis_font_size = 16 - self.label_font_size = 18 - self.title_font_size = 20 - self.text_size = 22 - - self.fig = figure(1, facecolor="w", figsize=(12,9)) - self.sp = self.fig.add_subplot(1,1,1) - self.pl = self.sp.plot(range(100), 100*[1,]) - - params = {'backend': 'ps', - 'xtick.labelsize': self.axis_font_size, - 'ytick.labelsize': self.axis_font_size, - 'text.usetex': False} - rcParams.update(params) - - self.sp.set_title(("FFT"), fontsize=self.title_font_size, fontweight="bold") - self.sp.set_xlabel("Frequency (Hz)", fontsize=self.label_font_size, fontweight="bold") - self.sp.set_ylabel("Magnitude (dB)", fontsize=self.label_font_size, fontweight="bold") - self.text_alpha = figtext(0.10, 0.94, ('Moving average alpha: %s' % alpha), weight="heavy", size=self.text_size) - - self.cfreqs = list() - self.freqrange = list() - self.data = list() #array('f') - - self.alpha = alpha - - self.index = 0 - self.full = False - self.last_cfreq = 0 - - self.sample_rate = sample_rate - self.percent = (1.0-percent)/2.0 - - def parse(self, msg): - self.center_freq = msg.arg1() - self.vlen = int(msg.arg2()) - assert(msg.length() == self.vlen * gr.sizeof_float) - - - if(self.center_freq < self.last_cfreq): - print "Plotting spectrum\n" - self.full = True - - self.pl[0].set_data([self.freqrange, self.data]) - self.sp.set_ylim([min(self.data), max(self.data)]) - self.sp.set_xlim([min(self.freqrange), max(self.freqrange)]) - draw() - - self.index = 0 - del self.freqrange - self.freqrange = list() - #raw_input() - - self.last_cfreq = self.center_freq - - startind = int(self.percent * self.vlen) - endind = int((1.0 - self.percent) * self.vlen) - - fstep = self.sample_rate / self.vlen - f = [self.center_freq - self.sample_rate/2.0 + i*fstep for i in range(startind, endind)] - self.freqrange += f - - t = msg.to_string() - d = struct.unpack('%df' % (self.vlen,), t) - - if self.full: - for i in range(startind, endind): - self.data[self.index] = (1.0-self.alpha)*self.data[self.index] + (self.alpha)*d[i] - self.index += 1 - else: - self.data += [di for di in d[startind:endind]] - - -class my_top_block(gr.top_block): - - def __init__(self): - gr.top_block.__init__(self) - - usage = "usage: %prog [options] host min_freq max_freq" - parser = OptionParser(option_class=eng_option, usage=usage) - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("", "--tune-delay", type="eng_float", default=5e-5, metavar="SECS", - help="time to delay (in seconds) after changing frequency [default=%default]") - parser.add_option("", "--dwell-delay", type="eng_float", default=50e-5, metavar="SECS", - help="time to dwell (in seconds) at a given frequncy [default=%default]") - parser.add_option("-F", "--fft-size", type="int", default=256, - help="specify number of FFT bins [default=%default]") - parser.add_option("-d", "--decim", type="intx", default=16, - help="set decimation to DECIM [default=%default]") - parser.add_option("", "--real-time", action="store_true", default=False, - help="Attempt to enable real-time scheduling") - - (options, args) = parser.parse_args() - if len(args) != 3: - parser.print_help() - sys.exit(1) - - self.address = args[0] - self.min_freq = eng_notation.str_to_num(args[1]) - self.max_freq = eng_notation.str_to_num(args[2]) - - self.decim = options.decim - self.gain = options.gain - - if self.min_freq > self.max_freq: - self.min_freq, self.max_freq = self.max_freq, self.min_freq # swap them - - self.fft_size = options.fft_size - - if not options.real_time: - realtime = False - else: - # Attempt to enable realtime scheduling - r = gr.enable_realtime_scheduling() - if r == gr.RT_OK: - realtime = True - else: - realtime = False - print "Note: failed to enable realtime scheduling" - - adc_rate = 102.4e6 - self.int_rate = adc_rate / self.decim - print "Sampling rate: ", self.int_rate - - # build graph - self.port = 10001 - self.src = msdd.source_simple(self.address, self.port) - self.src.set_decim_rate(self.decim) - - self.set_gain(self.gain) - self.set_freq(self.min_freq) - - s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self.fft_size) - - mywindow = window.blackmanharris(self.fft_size) - fft = gr.fft_vcc(self.fft_size, True, mywindow, True) - power = 0 - for tap in mywindow: - power += tap*tap - - norm = gr.multiply_const_cc(1.0/self.fft_size) - c2mag = gr.complex_to_mag_squared(self.fft_size) - - # FIXME the log10 primitive is dog slow - log = gr.nlog10_ff(10, self.fft_size, - -20*math.log10(self.fft_size)-10*math.log10(power/self.fft_size)) - - # Set the freq_step to % of the actual data throughput. - # This allows us to discard the bins on both ends of the spectrum. - self.percent = 0.4 - - self.freq_step = self.percent * self.int_rate - self.min_center_freq = self.min_freq + self.freq_step/2 - nsteps = math.ceil((self.max_freq - self.min_freq) / self.freq_step) - self.max_center_freq = self.min_center_freq + (nsteps * self.freq_step) - - self.next_freq = self.min_center_freq - - tune_delay = max(0, int(round(options.tune_delay * self.int_rate / self.fft_size))) # in fft_frames - dwell_delay = max(1, int(round(options.dwell_delay * self.int_rate / self.fft_size))) # in fft_frames - - self.msgq = gr.msg_queue(16) - self._tune_callback = tune(self) # hang on to this to keep it from being GC'd - stats = gr.bin_statistics_f(self.fft_size, self.msgq, - self._tune_callback, tune_delay, dwell_delay) - - # FIXME leave out the log10 until we speed it up - self.connect(self.src, s2v, fft, c2mag, log, stats) - - - def set_next_freq(self): - target_freq = self.next_freq - self.next_freq = self.next_freq + self.freq_step - if self.next_freq >= self.max_center_freq: - self.next_freq = self.min_center_freq - - if not self.set_freq(target_freq): - print "Failed to set frequency to", target_freq - - return target_freq - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - """ - return self.src.set_rx_freq(0, target_freq) - - - def set_gain(self, gain): - self.src.set_pga(0, gain) - - -def main_loop(tb): - msgparser = parse_msg(tb.int_rate, tb.percent) - - while 1: - - # Get the next message sent from the C++ code (blocking call). - # It contains the center frequency and the mag squared of the fft - msgparser.parse(tb.msgq.delete_head()) - - # Print center freq so we know that something is happening... - print msgparser.center_freq - - # FIXME do something useful with the data... - - # m.data are the mag_squared of the fft output (they are in the - # standard order. I.e., bin 0 == DC.) - # You'll probably want to do the equivalent of "fftshift" on them - # m.raw_data is a string that contains the binary floats. - # You could write this as binary to a file. - - -if __name__ == '__main__': - tb = my_top_block() - try: - tb.start() # start executing flow graph in another thread... - main_loop(tb) - - except KeyboardInterrupt: - pass diff --git a/gr-msdd6000/src/python-examples/msdd_spectrum_waterfall.py b/gr-msdd6000/src/python-examples/msdd_spectrum_waterfall.py deleted file mode 100755 index 05f047e11..000000000 --- a/gr-msdd6000/src/python-examples/msdd_spectrum_waterfall.py +++ /dev/null @@ -1,306 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2008 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru, eng_notation, optfir, window -from gnuradio import msdd -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import sys -import math -import struct -from pylab import * -from numpy import array -import time - -matplotlib.interactive(True) -matplotlib.use('TkAgg') - -class tune(gr.feval_dd): - """ - This class allows C++ code to callback into python. - """ - def __init__(self, tb): - gr.feval_dd.__init__(self) - self.tb = tb - - def eval(self, ignore): - """ - This method is called from gr.bin_statistics_f when it wants to change - the center frequency. This method tunes the front end to the new center - frequency, and returns the new frequency as its result. - """ - try: - # We use this try block so that if something goes wrong from here - # down, at least we'll have a prayer of knowing what went wrong. - # Without this, you get a very mysterious: - # - # terminate called after throwing an instance of 'Swig::DirectorMethodException' - # Aborted - # - # message on stderr. Not exactly helpful ;) - - new_freq = self.tb.set_next_freq() - return new_freq - - except Exception, e: - print "tune: Exception: ", e - - -class parse_msg(object): - def __init__(self, sample_rate, percent): - self.axis_font_size = 16 - self.label_font_size = 18 - self.title_font_size = 20 - self.text_size = 22 - - # Set up figures and subplots - self.fig = figure(1, facecolor="w", figsize=(12,9)) - self.sp = self.fig.add_subplot(1,1,1) - self.pl = self.sp.matshow(100*[range(100),]) - - params = {'xtick.labelsize': self.axis_font_size, - 'ytick.labelsize': self.axis_font_size} - rcParams.update(params) - - # Throw up some title info - self.sp.set_title(("FFT"), fontsize=self.title_font_size, fontweight="bold") - self.sp.set_xlabel("Frequency (Hz)", fontsize=self.label_font_size, fontweight="bold") - self.sp.set_ylabel("Sample index (should be time)", fontsize=self.label_font_size, fontweight="bold") - - self.freqrange = list() - self.data = list() - self.data3 = list() - - self.index = 0 - self.last_cfreq = 0 - - # So we know how to splice the data - self.sample_rate = sample_rate - self.percent = (1.0-percent)/2.0 - - def parse(self, msg): - self.center_freq = msg.arg1() # read the current center frequency - self.vlen = int(msg.arg2()) # read the length of the data set received - - # wait until we wrap around before plotting the entire collected band - if(self.center_freq < self.last_cfreq): - #print "Plotting spectrum\n" - - # If we have 100 sets, start dropping the oldest - if(len(self.data3) > 100): - self.data3.pop(0) - self.data3.append(self.data) - - # add the new data to the plot - self.pl.set_data(self.data3) - draw() - - # reset lists to collect next round - self.index = 0 - del self.freqrange - self.freqrange = list() - del self.data - self.data = list() - #raw_input() - - self.last_cfreq = self.center_freq - - startind = int(self.percent * self.vlen) - endind = int((1.0 - self.percent) * self.vlen) - - fstep = self.sample_rate / self.vlen - f = [self.center_freq - self.sample_rate/2.0 + i*fstep for i in range(startind, endind)] - self.freqrange += f - - t = msg.to_string(); - - d = struct.unpack('%df' % (self.vlen,), t) - - self.data += [di for di in d[startind:endind]] - - -class my_top_block(gr.top_block): - def __init__(self): - gr.top_block.__init__(self) - - # Build an options parser to bring in information from the user on usage - usage = "usage: %prog [options] host min_freq max_freq" - parser = OptionParser(option_class=eng_option, usage=usage) - parser.add_option("-g", "--gain", type="eng_float", default=32, - help="set gain in dB (default is midpoint)") - parser.add_option("", "--tune-delay", type="eng_float", default=5e-5, metavar="SECS", - help="time to delay (in seconds) after changing frequency [default=%default]") - parser.add_option("", "--dwell-delay", type="eng_float", default=50e-5, metavar="SECS", - help="time to dwell (in seconds) at a given frequncy [default=%default]") - parser.add_option("-F", "--fft-size", type="int", default=256, - help="specify number of FFT bins [default=%default]") - parser.add_option("-d", "--decim", type="intx", default=16, - help="set decimation to DECIM [default=%default]") - parser.add_option("", "--real-time", action="store_true", default=False, - help="Attempt to enable real-time scheduling") - - (options, args) = parser.parse_args() - if len(args) != 3: - parser.print_help() - sys.exit(1) - - # get user-provided info on address of MSDD and frequency to sweep - self.address = args[0] - self.min_freq = eng_notation.str_to_num(args[1]) - self.max_freq = eng_notation.str_to_num(args[2]) - - self.decim = options.decim - self.gain = options.gain - - if self.min_freq > self.max_freq: - self.min_freq, self.max_freq = self.max_freq, self.min_freq # swap them - - self.fft_size = options.fft_size - - if not options.real_time: - realtime = False - else: - # Attempt to enable realtime scheduling - r = gr.enable_realtime_scheduling() - if r == gr.RT_OK: - realtime = True - else: - realtime = False - print "Note: failed to enable realtime scheduling" - - # Sampling rate is hardcoded and cannot be read off device - adc_rate = 102.4e6 - self.int_rate = adc_rate / self.decim - print "Sampling rate: ", self.int_rate - - # build graph - self.port = 10001 # required port for UDP packets - - # which board, op mode, adx, port -# self.src = msdd.source_c(0, 1, self.address, self.port) # build source object - - self.conv = gr.interleaved_short_to_complex(); - - self.src = msdd.source_simple(self.address,self.port); - self.src.set_decim_rate(self.decim) # set decimation rate -# self.src.set_desired_packet_size(0, 1460) # set packet size to collect - - self.set_gain(self.gain) # set receiver's attenuation - self.set_freq(self.min_freq) # set receiver's rx frequency - - # restructure into vector format for FFT input - s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self.fft_size) - - # set up FFT processing block - mywindow = window.blackmanharris(self.fft_size) - fft = gr.fft_vcc(self.fft_size, True, mywindow, True) - power = 0 - for tap in mywindow: - power += tap*tap - - # calculate magnitude squared of output of FFT - c2mag = gr.complex_to_mag_squared(self.fft_size) - - # FIXME the log10 primitive is dog slow - log = gr.nlog10_ff(10, self.fft_size, - -20*math.log10(self.fft_size)-10*math.log10(power/self.fft_size)) - - # Set the freq_step to % of the actual data throughput. - # This allows us to discard the bins on both ends of the spectrum. - self.percent = 0.4 - - # Calculate the frequency steps to use in the collection over the whole bandwidth - self.freq_step = self.percent * self.int_rate - self.min_center_freq = self.min_freq + self.freq_step/2 - nsteps = math.ceil((self.max_freq - self.min_freq) / self.freq_step) - self.max_center_freq = self.min_center_freq + (nsteps * self.freq_step) - - self.next_freq = self.min_center_freq - - # use these values to set receiver settling time between samples and sampling time - # the default values provided seem to work well with the MSDD over 100 Mbps ethernet - tune_delay = max(0, int(round(options.tune_delay * self.int_rate / self.fft_size))) # in fft_frames - dwell_delay = max(1, int(round(options.dwell_delay * self.int_rate / self.fft_size))) # in fft_frames - - # set up message callback routine to get data from bin_statistics_f block - self.msgq = gr.msg_queue(16) - self._tune_callback = tune(self) # hang on to this to keep it from being GC'd - - # FIXME this block doesn't like to work with negatives because of the "d_max[i]=0" on line - # 151 of gr_bin_statistics_f.cc file. Set this to -10000 or something to get it to work. - stats = gr.bin_statistics_f(self.fft_size, self.msgq, - self._tune_callback, tune_delay, dwell_delay) - - # FIXME there's a concern over the speed of the log calculation - # We can probably calculate the log inside the stats block - self.connect(self.src, self.conv, s2v, fft, c2mag, log, stats) - - - def set_next_freq(self): - ''' Find and set the next frequency of the reciver. After going past the maximum frequency, - the frequency is wrapped around to the start again''' - target_freq = self.next_freq - self.next_freq = self.next_freq + self.freq_step - if self.next_freq >= self.max_center_freq: - self.next_freq = self.min_center_freq - - if not self.set_freq(target_freq): - print "Failed to set frequency to", target_freq - - return target_freq - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - """ - return self.src.set_rx_freq(0, target_freq) - - - def set_gain(self, gain): - self.src.set_pga(0, gain) - - -def main_loop(tb): - # Set up parser to get data from stats block and display them. - msgparser = parse_msg(tb.int_rate, tb.percent) - - while 1: - # Get the next message sent from the C++ code (blocking call). - # It contains the center frequency and the mag squared of the fft - d = tb.msgq.delete_head(); - print d.to_string(); - msgparser.parse(d) - #print msgparser.center_freq - -if __name__ == '__main__': - tb = my_top_block() - try: - tb.start() # start executing flow graph in another thread... - main_loop(tb) - - except KeyboardInterrupt: - pass diff --git a/gr-msdd6000/src/python-examples/new_msdd_fft.py b/gr-msdd6000/src/python-examples/new_msdd_fft.py deleted file mode 100755 index 782ecb66e..000000000 --- a/gr-msdd6000/src/python-examples/new_msdd_fft.py +++ /dev/null @@ -1,299 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2004,2005,2007,2008,2010 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp -from gnuradio import msdd -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2, form, slider -from optparse import OptionParser -import wx -import sys -import numpy - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - return (0, 0) - - -class app_top_block(stdgui2.std_top_block): - def __init__(self, frame, panel, vbox, argv): - stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv) - - self.frame = frame - self.panel = panel - - parser = OptionParser(option_class=eng_option) - parser.add_option("-w", "--which", type="int", default=0, - help="select which USRP (0, 1, ...) default is %default", - metavar="NUM") - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="select USRP Rx side A or B (default=first one with a daughterboard)") - parser.add_option("-A", "--antenna", default=None, - help="select Rx Antenna (only on RFX-series boards)") - parser.add_option("-d", "--decim", type="int", default=16, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=None, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-W", "--waterfall", action="store_true", default=False, - help="Enable waterfall display") - parser.add_option("-8", "--width-8", action="store_true", default=False, - help="Enable 8-bit samples across USB") - parser.add_option( "--no-hb", action="store_true", default=False, - help="don't use halfband filter in usrp") - parser.add_option("-S", "--oscilloscope", action="store_true", default=False, - help="Enable oscilloscope display") - parser.add_option("", "--avg-alpha", type="eng_float", default=1e-1, - help="Set fftsink averaging factor, default=[%default]") - parser.add_option("", "--ref-scale", type="eng_float", default=13490.0, - help="Set dBFS=0dB input value, default=[%default]") - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - self.options = options - self.show_debug_info = True - - # build the graph - if options.no_hb or (options.decim<8): - #Min decimation of this firmware is 4. - #contains 4 Rx paths without halfbands and 0 tx paths. - self.fpga_filename="std_4rx_0tx.rbf" -# self.u = usrp.source_c(which=options.which, decim_rate=options.decim, fpga_filename=self.fpga_filename) - self.u = msdd.source_simple("192.168.1.200",0); - else: - #Min decimation of standard firmware is 8. - #standard fpga firmware "std_2rxhb_2tx.rbf" - #contains 2 Rx paths with halfband filters and 2 tx paths (the default) - #self.u = usrp.source_c(which=options.which, decim_rate=options.decim) - self.u = msdd.source_simple("192.168.1.200",0); - - - input_rate = self.u.adc_freq() / self.u.decim_rate() - - if options.waterfall: - self.scope = \ - waterfallsink2.waterfall_sink_c (panel, fft_size=1024, sample_rate=input_rate) - elif options.oscilloscope: - self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate) - else: - self.scope = fftsink2.fft_sink_c (panel, fft_size=1024, sample_rate=input_rate, - ref_scale=options.ref_scale, ref_level=0.0, y_divs = 10, - avg_alpha=options.avg_alpha) - - self.conv = gr.interleaved_short_to_complex(); - self.connect(self.u, self.conv, self.scope) - - self._build_gui(vbox) - self._setup_events() - - # set initial values - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - #g = self.subdev.gain_range() - #g = self.u.gain_range() - g = [0,10] - options.gain = float(g[0]+g[1])/2 - - if options.freq is None: - # if no freq was specified, use the mid-point - #r = self.subdev.freq_range() - #r = self.u.freq_range() - r = [30e6, 6e9] - options.freq = float(r[0]+r[1])/2 - - self.set_gain(options.gain) - - if options.antenna is not None: - print "Selecting antenna %s" % (options.antenna,) - self.subdev.select_rx_antenna(options.antenna) - - if self.show_debug_info: - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - self.myform['dbname'].set_value("no subdevs used") - self.myform['baseband'].set_value(0) - self.myform['ddc'].set_value(0) - - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - - def _set_status_msg(self, msg): - self.frame.GetStatusBar().SetStatusText(msg, 0) - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - vbox.Add(self.scope.win, 10, wx.EXPAND) - - # add control area at the bottom - self.myform = myform = form.form() - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0, 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Center freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0, 0) - #g = self.subdev.gain_range() - #g = self.u.gain_range() - g = [0,10] - myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, - min=int(g[0]), max=int(g[1]), - callback=self.set_gain) - - hbox.Add((5,0), 0, 0) - vbox.Add(hbox, 0, wx.EXPAND) - - self._build_subpanel(vbox) - - def _build_subpanel(self, vbox_arg): - # build a secondary information panel (sometimes hidden) - - # FIXME figure out how to have this be a subpanel that is always - # created, but has its visibility controlled by foo.Show(True/False) - - def _form_set_decim(kv): - return self.set_decim(kv['decim']) - - if not(self.show_debug_info): - return - - panel = self.panel - vbox = vbox_arg - myform = self.myform - - #panel = wx.Panel(self.panel, -1) - #vbox = wx.BoxSizer(wx.VERTICAL) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - - myform['decim'] = form.int_field( - parent=panel, sizer=hbox, label="Decim", - callback=myform.check_input_and_call(_form_set_decim, self._set_status_msg)) - - hbox.Add((5,0), 1) - myform['fs@usb'] = form.static_float_field( - parent=panel, sizer=hbox, label="Fs@gigE") - - hbox.Add((5,0), 1) - myform['dbname'] = form.static_text_field( - parent=panel, sizer=hbox) - - hbox.Add((5,0), 1) - myform['baseband'] = form.static_float_field( - parent=panel, sizer=hbox, label="Analog BB") - - hbox.Add((5,0), 1) - myform['ddc'] = form.static_float_field( - parent=panel, sizer=hbox, label="DDC") - - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - #r = self.u.tune(0, self.subdev, target_freq) - r = self.u.set_rx_freq(0, target_freq) - - if r: - self.myform['freq'].set_value(target_freq) # update displayed value -# if self.show_debug_info: -# self.myform['baseband'].set_value(r.baseband_freq) -# self.myform['ddc'].set_value(r.dxc_freq) - if not self.options.waterfall and not self.options.oscilloscope: - self.scope.set_baseband_freq(target_freq) - return True - - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - self.u.set_pga(0,gain) - - def set_decim(self, decim): - ok = self.u.set_decim_rate(decim) - if not ok: - print "set_decim failed" - input_rate = self.u.adc_freq() / self.u.decim_rate() - self.scope.set_sample_rate(input_rate) - if self.show_debug_info: # update displayed values - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - return ok - - def _setup_events(self): - if not self.options.waterfall and not self.options.oscilloscope: - self.scope.win.Bind(wx.EVT_LEFT_DCLICK, self.evt_left_dclick) - - def evt_left_dclick(self, event): - (ux, uy) = self.scope.win.GetXY(event) - if event.CmdDown(): - # Re-center on maximum power - points = self.scope.win._points - if self.scope.win.peak_hold: - if self.scope.win.peak_vals is not None: - ind = numpy.argmax(self.scope.win.peak_vals) - else: - ind = int(points.shape()[0]/2) - else: - ind = numpy.argmax(points[:,1]) - (freq, pwr) = points[ind] - target_freq = freq/self.scope.win._scale_factor - print ind, freq, pwr - self.set_freq(target_freq) - else: - # Re-center on clicked frequency - target_freq = ux/self.scope.win._scale_factor - self.set_freq(target_freq) - - -def main (): - app = stdgui2.stdapp(app_top_block, "USRP FFT", nstatus=1) - app.MainLoop() - -if __name__ == '__main__': - main () diff --git a/gr-msdd6000/src/python-examples/ofdm/benchmark_ofdm_rx.py b/gr-msdd6000/src/python-examples/ofdm/benchmark_ofdm_rx.py deleted file mode 100755 index deb82e111..000000000 --- a/gr-msdd6000/src/python-examples/ofdm/benchmark_ofdm_rx.py +++ /dev/null @@ -1,184 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2006, 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, blks2 -from gnuradio import msdd -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from optparse import OptionParser - -import struct, sys - -# from current dir -from receive_path import receive_path - -class my_top_block(gr.top_block): - def __init__(self, address, callback, options): - gr.top_block.__init__(self) - - self._address = address - self._rx_freq = options.rx_freq # receiver's center frequency - self._rx_gain = options.rx_gain # receiver's gain - self._decim = options.decim # Decimating rate for the USRP (prelim) - - if self._rx_freq is None: - sys.stderr.write("-f FREQ or --freq FREQ or --rx-freq FREQ must be specified\n") - raise SystemExit - - # Set up USRP source - self._setup_source() - - #taps = gr.firdes.low_pass(1, 1, 0.4, 0.2) - #self.resample = gr.rational_resampler_base_ccf(5, 8, taps) - self.resample = blks2.rational_resampler_ccf(5, 8) - - # Set up receive path - self.rxpath = receive_path(callback, options) - - self.connect(self.src, self.resample, self.rxpath) - #self.connect(self.src, gr.file_sink(gr.sizeof_gr_complex, "receive.dat")) - #self.connect(self.resample, gr.file_sink(gr.sizeof_gr_complex, "resampled.dat")) - - def _setup_source(self): - # build graph - self._port = 10001 - self.src = msdd.source_c(0, 1, self._address, self._port) - self.src.set_decim_rate(self._decim) - self.src.set_desired_packet_size(0, 1460) - - self.set_gain(self._rx_gain) - self.set_freq(self._rx_freq) - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - """ - r = self.src.set_rx_freq(0, target_freq) - if r: - return True - return False - - def set_gain(self, gain): - """ - Sets the analog gain in the USRP - """ - return self.src.set_pga(0, gain) - - def decim(self): - return self._decim - - def add_options(normal, expert): - """ - Adds usrp-specific options to the Options Parser - """ - add_freq_option(normal) - normal.add_option("", "--rx-gain", type="eng_float", default=32, metavar="GAIN", - help="set receiver gain in dB [default=%default].") - normal.add_option("-v", "--verbose", action="store_true", default=False) - - expert.add_option("", "--rx-freq", type="eng_float", default=None, - help="set Rx frequency to FREQ [default=%default]", metavar="FREQ") - expert.add_option("-d", "--decim", type="intx", default=128, - help="set fpga decimation rate to DECIM [default=%default]") - expert.add_option("", "--snr", type="eng_float", default=30, - help="set the SNR of the channel in dB [default=%default]") - - # Make a static method to call before instantiation - add_options = staticmethod(add_options) - -def add_freq_option(parser): - """ - Hackery that has the -f / --freq option set both tx_freq and rx_freq - """ - def freq_callback(option, opt_str, value, parser): - parser.values.rx_freq = value - parser.values.tx_freq = value - - if not parser.has_option('--freq'): - parser.add_option('-f', '--freq', type="eng_float", - action="callback", callback=freq_callback, - help="set Tx and/or Rx frequency to FREQ [default=%default]", - metavar="FREQ") - -# ///////////////////////////////////////////////////////////////////////////// -# main -# ///////////////////////////////////////////////////////////////////////////// - -def main(): - - global n_rcvd, n_right - - n_rcvd = 0 - n_right = 0 - - def rx_callback(ok, payload): - global n_rcvd, n_right - n_rcvd += 1 - (pktno,) = struct.unpack('!H', payload[0:2]) - if ok: - n_right += 1 - print "ok: %r \t pktno: %d \t n_rcvd: %d \t n_right: %d" % (ok, pktno, n_rcvd, n_right) - - if 0: - printlst = list() - for x in payload[2:]: - t = hex(ord(x)).replace('0x', '') - if(len(t) == 1): - t = '0' + t - printlst.append(t) - printable = ''.join(printlst) - - print printable - print "\n" - - usage = "usage: %prog [options] host" - parser = OptionParser(usage=usage, option_class=eng_option, conflict_handler="resolve") - expert_grp = parser.add_option_group("Expert") - parser.add_option("","--discontinuous", action="store_true", default=False, - help="enable discontinuous") - - my_top_block.add_options(parser, expert_grp) - receive_path.add_options(parser, expert_grp) - blks2.ofdm_mod.add_options(parser, expert_grp) - blks2.ofdm_demod.add_options(parser, expert_grp) - - (options, args) = parser.parse_args () - address = args[0] - - # build the graph - tb = my_top_block(address, rx_callback, options) - - #r = gr.enable_realtime_scheduling() - #if r != gr.RT_OK: - # print "Warning: failed to enable realtime scheduling" - - tb.start() # start flow graph - tb.wait() # wait for it to finish - -if __name__ == '__main__': - try: - main() - except KeyboardInterrupt: - pass diff --git a/gr-msdd6000/src/python-examples/ofdm/gr_plot_ofdm.py b/gr-msdd6000/src/python-examples/ofdm/gr_plot_ofdm.py deleted file mode 100755 index 0bca41037..000000000 --- a/gr-msdd6000/src/python-examples/ofdm/gr_plot_ofdm.py +++ /dev/null @@ -1,268 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -import scipy, pylab, math -import struct, sys -from pylab import * -from matplotlib.font_manager import fontManager, FontProperties -from optparse import OptionParser -from scipy import fftpack -from math import log10 - -matplotlib.interactive(True) -matplotlib.use('TkAgg') - -class draw_constellation: - def __init__(self, options): - derot_file = "ofdm_frame_sink_c.dat" - acq_file = "ofdm_frame_acq_c.dat" - fft_file = "fft_out_c.dat" - - self.h_derot_file = open(derot_file, "r") - self.h_acq_file = open(acq_file, "r") - self.h_fft_file = open(fft_file, "r") - - self.occ_tones = options.occ_tones - self.fft_size = options.fft_size - self.symbol = options.start - self.sample_rate = options.sample_rate - - self.axis_font_size = 16 - self.label_font_size = 18 - self.title_font_size = 20 - self.text_size = 22 - - # Setup PLOT - self.fig = figure(1, figsize=(14, 9), facecolor='w') - rcParams['xtick.labelsize'] = self.axis_font_size - rcParams['ytick.labelsize'] = self.axis_font_size - - self.text_sym = figtext(0.05, 0.95, ("Symbol: %s" % self.symbol), weight="heavy", size=self.text_size) - - self.make_plots() - - self.button_left_axes = self.fig.add_axes([0.45, 0.01, 0.05, 0.05], frameon=True) - self.button_left = Button(self.button_left_axes, "<") - self.button_left_callback = self.button_left.on_clicked(self.button_left_click) - - self.button_right_axes = self.fig.add_axes([0.50, 0.01, 0.05, 0.05], frameon=True) - self.button_right = Button(self.button_right_axes, ">") - self.button_right_callback = self.button_right.on_clicked(self.button_right_click) - - self.xlim = self.sp_eq.get_xlim() - - self.manager = get_current_fig_manager() - #connect('draw_event', self.zoom) - connect('key_press_event', self.click) - show() - - def get_data(self): - self.text_sym.set_text("Symbol: %d" % (self.symbol)) - - derot_data = scipy.fromfile(self.h_derot_file, dtype=scipy.complex64, count=self.occ_tones) - acq_data = scipy.fromfile(self.h_acq_file, dtype=scipy.complex64, count=self.occ_tones) - fft_data = scipy.fromfile(self.h_fft_file, dtype=scipy.complex64, count=self.fft_size) - if(len(acq_data) == 0): - print "End of File" - else: - self.acq_data_reals = [r.real for r in acq_data] - self.acq_data_imags = [i.imag for i in acq_data] - self.derot_data_reals = [r.real for r in derot_data] - self.derot_data_imags = [i.imag for i in derot_data] - - self.unequalized_angle = [math.atan2(x.imag, x.real) for x in fft_data] - self.equalized_angle = [math.atan2(x.imag, x.real) for x in acq_data] - self.derot_equalized_angle = [math.atan2(x.imag, x.real) for x in derot_data] - - self.time = [i*(1/self.sample_rate) for i in range(len(acq_data))] - ffttime = [i*(1/self.sample_rate) for i in range(len(fft_data))] - - self.freq = self.get_freq(ffttime, self.sample_rate) - - for i in range(len(fft_data)): - if(abs(fft_data[i]) == 0.0): - fft_data[i] = complex(1e-6,1e-6) - self.fft_data = [20*log10(abs(f)) for f in fft_data] - - def get_freq(self, time, sample_rate, T=1): - N = len(time) - Fs = 1.0 / (max(time) - min(time)) - Fn = 0.5 * sample_rate - freq = [-Fn + i*Fs for i in range(N)] - return freq - - def make_plots(self): - self.h_acq_file.seek(8*self.symbol*self.occ_tones, 0) - self.h_fft_file.seek(8*self.symbol*self.fft_size, 0) - self.h_derot_file.seek(8*self.symbol*self.occ_tones, 0) - - self.get_data() - - # Subplot: constellation of rotated symbols - self.sp_const = self.fig.add_subplot(4,1,1, position=[0.15, 0.55, 0.3, 0.35]) - self.sp_const.set_title(("Constellation"), fontsize=self.title_font_size, fontweight="bold") - self.sp_const.set_xlabel("Inphase", fontsize=self.label_font_size, fontweight="bold") - self.sp_const.set_ylabel("Qaudrature", fontsize=self.label_font_size, fontweight="bold") - self.plot_const = plot(self.acq_data_reals, self.acq_data_imags, 'bo') - self.plot_const += plot(self.derot_data_reals, self.derot_data_imags, 'ro') - self.sp_const.axis([-2, 2, -2, 2]) - - # Subplot: unequalized angle - self.sp_uneq = self.fig.add_subplot(4,2,1, position=[0.575, 0.55, 0.3, 0.35]) - self.sp_uneq.set_title(("Unequalized Angle"), fontsize=self.title_font_size, fontweight="bold") - self.sp_uneq.set_xlabel("Time (s)", fontsize=self.label_font_size, fontweight="bold") - self.sp_uneq.set_ylabel("Angle", fontsize=self.label_font_size, fontweight="bold") - uneqscale = range(len(self.unequalized_angle)) - self.plot_uneq = plot(uneqscale, self.unequalized_angle, 'bo') - - # Subplot: equalized angle - self.sp_eq = self.fig.add_subplot(4,1,2, position=[0.15, 0.1, 0.3, 0.35]) - self.sp_eq.set_title(("Equalized Angle"), fontsize=self.title_font_size, fontweight="bold") - self.sp_eq.set_xlabel("Time (s)", fontsize=self.label_font_size, fontweight="bold") - self.sp_eq.set_ylabel("Angle", fontsize=self.label_font_size, fontweight="bold") - eqscale = range(len(self.equalized_angle)) - self.plot_eq = plot(eqscale, self.equalized_angle, 'bo') - self.plot_eq += plot(eqscale, self.derot_equalized_angle, 'ro', markersize=4) - - # Subplot: FFT - self.sp_fft = self.fig.add_subplot(4,2,2, position=[0.575, 0.1, 0.3, 0.35]) - self.sp_fft.set_title(("FFT"), fontsize=self.title_font_size, fontweight="bold") - self.sp_fft.set_xlabel("Frequency (MHz)", fontsize=self.label_font_size, fontweight="bold") - self.sp_fft.set_ylabel("Power (dBm)", fontsize=self.label_font_size, fontweight="bold") - self.plot_fft = plot(self.freq, self.fft_data, '-bo') - - draw() - - def update_plots(self): - eqscale = range(len(self.equalized_angle)) - uneqscale = range(len(self.unequalized_angle)) - self.plot_eq[0].set_data([eqscale, self.equalized_angle]) - self.plot_eq[1].set_data([eqscale, self.derot_equalized_angle]) - self.plot_uneq[0].set_data([uneqscale, self.unequalized_angle]) - self.sp_eq.set_ylim([-4, 4]) - self.sp_uneq.set_ylim([-4, 4]) - - #self.sp_iq.axis([min(self.time), max(self.time), - # 1.5*min([min(self.acq_data_reals), min(self.acq_data_imags)]), - # 1.5*max([max(self.acq_data_reals), max(self.acq_data_imags)])]) - - self.plot_const[0].set_data([self.acq_data_reals, self.acq_data_imags]) - self.plot_const[1].set_data([self.derot_data_reals, self.derot_data_imags]) - self.sp_const.axis([-2, 2, -2, 2]) - - self.plot_fft[0].set_data([self.freq, self.fft_data]) - - draw() - - def zoom(self, event): - newxlim = self.sp_eq.get_xlim() - if(newxlim != self.xlim): - self.xlim = newxlim - r = self.reals[int(ceil(self.xlim[0])) : int(ceil(self.xlim[1]))] - i = self.imags[int(ceil(self.xlim[0])) : int(ceil(self.xlim[1]))] - - self.plot_const[0].set_data(r, i) - self.sp_const.axis([-2, 2, -2, 2]) - self.manager.canvas.draw() - draw() - - def click(self, event): - forward_valid_keys = [" ", "down", "right"] - backward_valid_keys = ["up", "left"] - - if(find(event.key, forward_valid_keys)): - self.step_forward() - - elif(find(event.key, backward_valid_keys)): - self.step_backward() - - def button_left_click(self, event): - self.step_backward() - - def button_right_click(self, event): - self.step_forward() - - def step_forward(self): - self.symbol += 1 - self.get_data() - self.update_plots() - - def step_backward(self): - # Step back in file position - self.symbol -= 1 - if(self.h_acq_file.tell() >= 16*self.occ_tones): - self.h_acq_file.seek(-16*self.occ_tones, 1) - else: - self.symbol = 0 - self.h_acq_file.seek(-self.h_acq_file.tell(),1) - - - if(self.h_derot_file.tell() >= 16*self.occ_tones): - self.h_derot_file.seek(-16*self.occ_tones, 1) - else: - self.symbol = 0 - self.h_derot_file.seek(-self.h_derot_file.tell(),1) - - - if(self.h_fft_file.tell() >= 16*self.fft_size): - self.h_fft_file.seek(-16*self.fft_size, 1) - else: - self.symbol = 0 - self.h_fft_file.seek(-self.h_fft_file.tell(),1) - - self.get_data() - self.update_plots() - - - -#FIXME: there must be a way to do this with a Python builtin -def find(item_in, list_search): - for l in list_search: - if item_in == l: - return True - return False - -def main(): - usage="%prog: [options]" - - parser = OptionParser(conflict_handler="resolve", usage=usage) - parser.add_option("", "--fft-size", type="int", default=512, - help="Specify the size of the FFT [default=%default]") - parser.add_option("", "--occ-tones", type="int", default=200, - help="Specify the number of occupied tones [default=%default]") - parser.add_option("-s", "--start", type="int", default=0, - help="Specify the starting symbol to plot [default=%default]") - parser.add_option("-R", "--sample-rate", type="float", default=1.0, - help="Set the sampler rate of the data [default=%default]") - - (options, args) = parser.parse_args () - - dc = draw_constellation(options) - -if __name__ == "__main__": - try: - main() - except KeyboardInterrupt: - pass - - - diff --git a/gr-msdd6000/src/python-examples/ofdm/receive_path.py b/gr-msdd6000/src/python-examples/ofdm/receive_path.py deleted file mode 100644 index 11c714aaf..000000000 --- a/gr-msdd6000/src/python-examples/ofdm/receive_path.py +++ /dev/null @@ -1,102 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2005,2006 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru, blks2 -from gnuradio import usrp -from gnuradio import eng_notation -import copy -import sys - -# ///////////////////////////////////////////////////////////////////////////// -# receive path -# ///////////////////////////////////////////////////////////////////////////// - -class receive_path(gr.hier_block2): - def __init__(self, rx_callback, options): - - gr.hier_block2.__init__(self, "receive_path", - gr.io_signature(1, 1, gr.sizeof_gr_complex), # Input signature - gr.io_signature(0, 0, 0)) # Output signature - - - options = copy.copy(options) # make a copy so we can destructively modify - - self._verbose = options.verbose - self._log = options.log - self._rx_callback = rx_callback # this callback is fired when there's a packet available - - # receiver - self.ofdm_rx = \ - blks2.ofdm_demod(options, callback=self._rx_callback) - - # Carrier Sensing Blocks - alpha = 0.001 - thresh = 30 # in dB, will have to adjust - self.probe = gr.probe_avg_mag_sqrd_c(thresh,alpha) - - self.connect(self, self.ofdm_rx) - self.connect(self.ofdm_rx, self.probe) - - # Display some information about the setup - if self._verbose: - self._print_verbage() - - def carrier_sensed(self): - """ - Return True if we think carrier is present. - """ - #return self.probe.level() > X - return self.probe.unmuted() - - def carrier_threshold(self): - """ - Return current setting in dB. - """ - return self.probe.threshold() - - def set_carrier_threshold(self, threshold_in_db): - """ - Set carrier threshold. - - @param threshold_in_db: set detection threshold - @type threshold_in_db: float (dB) - """ - self.probe.set_threshold(threshold_in_db) - - - def add_options(normal, expert): - """ - Adds receiver-specific options to the Options Parser - """ - normal.add_option("-v", "--verbose", action="store_true", default=False) - expert.add_option("", "--log", action="store_true", default=False, - help="Log all parts of flow graph to files (CAUTION: lots of data)") - - # Make a static method to call before instantiation - add_options = staticmethod(add_options) - - - def _print_verbage(self): - """ - Prints information about the receive path - """ - pass diff --git a/gr-msdd6000/src/python-examples/playback_samples.m b/gr-msdd6000/src/python-examples/playback_samples.m deleted file mode 100644 index 332296e72..000000000 --- a/gr-msdd6000/src/python-examples/playback_samples.m +++ /dev/null @@ -1,12 +0,0 @@ -t = read_complex_binary('msdd.dat',10000000); - -fftsize=256; -w = [0:pi/fftsize:pi]; - -for i = 0:length(t)/fftsize - fftdata = fft(i*fftsize:i*fftsize+fftsize); - clear plot; - plot(w,fftdata); -endfor - -pause; diff --git a/gr-msdd6000/src/python-examples/read_complex_binary.m b/gr-msdd6000/src/python-examples/read_complex_binary.m deleted file mode 100644 index 67158b528..000000000 --- a/gr-msdd6000/src/python-examples/read_complex_binary.m +++ /dev/null @@ -1,48 +0,0 @@ -% -% Copyright 2001 Free Software Foundation, Inc. -% -% This file is part of GNU Radio -% -% GNU Radio is free software; you can redistribute it and/or modify -% it under the terms of the GNU General Public License as published by -% the Free Software Foundation; either version 3, or (at your option) -% any later version. -% -% GNU Radio is distributed in the hope that it will be useful, -% but WITHOUT ANY WARRANTY; without even the implied warranty of -% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -% GNU General Public License for more details. -% -% You should have received a copy of the GNU General Public License -% along with GNU Radio; see the file COPYING. If not, write to -% the Free Software Foundation, Inc., 51 Franklin Street, -% Boston, MA 02110-1301, USA. -% - -function v = read_complex_binary (filename, count) - - %% usage: read_complex_binary (filename, [count]) - %% - %% open filename and return the contents as a column vector, - %% treating them as 32 bit complex numbers - %% - - m = nargchk (1,2,nargin); - if (m) - usage (m); - end - - if (nargin < 2) - count = Inf; - end - - f = fopen (filename, 'rb'); - if (f < 0) - v = 0; - else - t = fread (f, [2, count], 'float'); - fclose (f); - v = t(1,:) + t(2,:)*i; - [r, c] = size (v); - v = reshape (v, c, r); - end diff --git a/gr-msdd6000/src/python_test/capture_tcp_one_set.py b/gr-msdd6000/src/python_test/capture_tcp_one_set.py deleted file mode 100644 index 7a106a63a..000000000 --- a/gr-msdd6000/src/python_test/capture_tcp_one_set.py +++ /dev/null @@ -1,156 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -port = 10000 -host = "10.45.4.46" -#host = "10.45.4.41" -myaddr = ('',myport); - -buf = 100000; - -TCPSock = socket(AF_INET,SOCK_STREAM); -TCPSock.bind(myaddr); -TCPSock.connect((host,port)); - -#f_mhz = 2647; # roof ofdm -if(len(sys.argv)!= 3): - print "usage: %s fc_ghz decim_pow2_exponent"%(sys.argv[0]); - sys.exit(-1); - -f_mhz = float(sys.argv[1])*1000; -decim = int(sys.argv[2]); - -#f_mhz = 3500; -#f_mhz = 2600; -f_hz = 0; # offset -gain = 0; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -samples = 65536; -#samples = 16777216; -samples = samples*4; #bytes of data we are requesting -samples=samples*2; -#decim = 2; #0-8 (3 => 2^3 = 8) -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -sets = 1; - -raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -TCPSock.send(data); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; -while(TCPSock): - if(state==0): - data = TCPSock.recv(4); - [opcode] = struct.unpack("<I", data); - print "Opcode = %d"%(opcode); - if(opcode==1): - state = 1; - - elif(state==1): - data = TCPSock.recv(7*4); - args = struct.unpack("<IIIIIII", data); - print ["reply_len", "freq_mhz", "offset_hz", "gain", "sample_bytes", "decim", "sets_remain"]; - print args; - IQ_bytes = args[0] - 7*4; - state =2; - - elif(state==2): - data = TCPSock.recv(4); - [i,q] = struct.unpack("<hh", data); - tmp = complex(i,q); - - re.append(i); - vals.append(tmp); - mags.append(abs(tmp)); - - - sample_count = sample_count + 1; -# print "sample count %d"%(sample_count) - - IQ_bytes = IQ_bytes - 4; - if(IQ_bytes < 4): - print "got all data (total %d)"%(sample_count); - print "remaining: %d"%(IQ_bytes); - break; - - -TCPSock.close(); - -print "done" -nmags = [] -for i in mags: - if i == 0: - i=1; - nmags.append(i); - - -subplot(2,1,1); -plot(nmags); -#plot(10*log10(nmags)); - -dlen = len(vals); -fftlen = (dlen-1024)/1024; - -fft_data = [] -for i in range(1, dlen-1025, 1024): - - t_in = []; - for ind in range(i, i+1024): - t_in.append(vals[ind]); - - #tmp = 20*log10(fftshift(fft(t_in))); - tmp = (fftshift(fft(t_in))); - - if(len(fft_data) == 0): - for ind in range(0,1024): - fft_data.append( tmp[ind] ); - else: - for ind in range(0,1024): - fft_data[ind] = fft_data[ind] + tmp[ind]; - -#fft_data = 20*log10(fftshift(fft(vals))); - - -subplot(2,1,2); -plot(fft_data); -show(); - -f = open(filename, "w"); -for sample in vals: - binchunk = struct.pack("<ff",float(sample.real), float(sample.imag) ); - f.write(binchunk); -f.close(); - - diff --git a/gr-msdd6000/src/python_test/flood_udp.py b/gr-msdd6000/src/python_test/flood_udp.py deleted file mode 100644 index e59208a7a..000000000 --- a/gr-msdd6000/src/python_test/flood_udp.py +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; - -msdd_port = 10001 -msdd_host = "10.45.4.43" - -my_udp_addr = ("10.45.1.229",10001); - -buf = 1024; - -#myport = random.randint(1025,65535); -#my_tcp_addr = ("10.45.1.229",myport); -#TCPSock = socket(AF_INET,SOCK_STREAM); -#TCPSock.bind(my_tcp_addr); -#TCPSock.connect((msdd_host,msdd_port)); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -SETS_STREAM = 0xffffffff; - -f_mhz = 2400; -f_hz = 1; -gain = 3; -samples = 512; -decim = 4; -#sets = 16; -sets = SETS_STREAM; -window = 3; -mode = 1; - - - -for first_byte in range(0,0xff): - for second_byte in range(0,0xff): - for third_byte in range(0,0xff): - data = struct.pack("!III", first_byte, second_byte,third_byte); - UDPSock.sendto(data, (msdd_host,msdd_port)) - - -# construct the 3 different request type packets -#fft_data = struct.pack("<IIIIIIIIII", 0x02, 0x20, f_mhz, f_hz, gain,window, samples, decim, mode,sets); -#raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); -#stat_data = struct.pack("!II", 0x0000, 0x0000) - -# send appropriate udp request packet - - - - - - - - - diff --git a/gr-msdd6000/src/python_test/halt.py b/gr-msdd6000/src/python_test/halt.py deleted file mode 100644 index 0285f7817..000000000 --- a/gr-msdd6000/src/python_test/halt.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.43" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -halt_data = struct.pack("<II", 0x04, 0x00); -halt_data = struct.pack("<II", 0x04, 0x00); - -data = halt_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - -UDPSock.close(); - - - diff --git a/gr-msdd6000/src/python_test/newtest.py b/gr-msdd6000/src/python_test/newtest.py deleted file mode 100644 index 9596a0675..000000000 --- a/gr-msdd6000/src/python_test/newtest.py +++ /dev/null @@ -1,140 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.43" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -#f_mhz = 3500; -#f_mhz = 3500; -f_mhz = 100; -f_hz = 0; -gain = 0; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -samples = 12000; -samples = samples*4; #bytes of data we are requesting - -decim = 2; #0-8 (3 => 2^3 = 8) -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -#raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain, samples, decim, sets); -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - -while(True): - print state; - if(state==0): - data = UDPSock.recv(4); - [opcode] = struct.unpack("<I", data); - print "Opcode = %d"%(opcode); - if(opcode==1): - - # if UDP mode and sets_stream requested, - # we do not get a header reply back, only data - if(sets == 0): - state = 1; - else: - state = 2; - - elif(state==1): - data = UDPSock.recv(7*4); - args = struct.unpack("<IIIIIII", data); - print ["reply_len", "freq_mhz", "offset_hz", "gain", "sample_bytes", "decim", "sets_remain"]; - print args; - IQ_bytes = args[0] - 7*4; - state =2; - - elif(state==2): - data = UDPSock.recv(4); - [i,q] = struct.unpack("<hh", data); - tmp = complex(i,q); - - re.append(i); - vals.append(tmp); - mags.append(abs(tmp)); - - - sample_count = sample_count + 1; -# print "sample count %d"%(sample_count) - - IQ_bytes = IQ_bytes - 4; - if(IQ_bytes < 4): - print "got all data (total %d)"%(sample_count); - print "remaining: %d"%(IQ_bytes); - break; - - -UDPSock.close(); - -print "done" -nmags = [] -for i in mags: - if i == 0: - i=1; - nmags.append(i); - - -subplot(2,1,1); -plot(20*log10(nmags)); - -fft_data = 20*log10(fftshift(fft(vals))); - -subplot(2,1,2); -plot(fft_data); -show(); - -f = open(filename, "w"); -for sample in vals: - binchunk = struct.pack("<ff",float(sample.real), float(sample.imag) ); - f.write(binchunk); -f.close(); - - diff --git a/gr-msdd6000/src/python_test/spectrogram.py b/gr-msdd6000/src/python_test/spectrogram.py deleted file mode 100644 index 015dd9105..000000000 --- a/gr-msdd6000/src/python_test/spectrogram.py +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/python - -fft_bins = 1024; -stride = 256; - -#filename = "output.dat"; -#decim = 4; -#Fs = (102.4/decim) * 1e6; - - -from gnuradio import gr; -from Numeric import *; -import FFT; -import numpy.fft; -from numpy import *; -from pylab import *; -import sys; - -if len(sys.argv) <2: - print "usage: %s filename <sample_rate_in_MSPS> <stride_samples>"%(sys.argv[0]); - sys.exit(-1); - -filename = sys.argv[1]; -fs = 0; -if(len(sys.argv)>2): - fs = float(sys.argv[2])*1000000; -print "opening %s.\n"%(filename); - -if(len(sys.argv)>=4): - stride = int(sys.argv[3]); - print "using stride = %d"%(stride); - -tb = gr.top_block(); -src = gr.file_source(gr.sizeof_gr_complex, filename, False) -sink = gr.vector_sink_c(); -tb.connect(src,sink); -tb.run(); - -data = sink.data(); -dataa = array(data); -datalen = len( data ); - -time_bins = (datalen - fft_bins) / stride; - -print "output vector :: fft_bins = %d, time_bins = %d\n"%(fft_bins,time_bins); - -start_idx = 0; - -b = numpy.zeros((time_bins, fft_bins), complex); -l = []; - -window = numpy.blackman(fft_bins); - -for i in range(0,time_bins): - - time_chunk = take( dataa, range(start_idx,start_idx + fft_bins), 0); - time_chunk = time_chunk * window; - fft_chunk = numpy.fft.fftshift(numpy.fft.fft(time_chunk)); - psd = 10*log10(fft_chunk * conj(fft_chunk)+0.001); - - b[i] = psd.real; - l.append( psd.real.tolist() ); - - start_idx = start_idx + stride; - -#c = array(b, 10); - -print b[0]; -c = array(b); -#l = c.tolist(); -print size(l); - -x = range(0,time_bins); -print size(x); -y = range(0,fft_bins); -print size(y); - -print size(l); - -contourf(l); -#contourf([x,y], l); -colorbar(); -show(); - -#print c[1,1]; - - diff --git a/gr-msdd6000/src/python_test/test_tcp.py b/gr-msdd6000/src/python_test/test_tcp.py deleted file mode 100755 index b02db815d..000000000 --- a/gr-msdd6000/src/python_test/test_tcp.py +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; - -myport = random.randint(1025,65535); - -port = 10000 -host = "10.45.4.43" -myaddr = ("10.45.1.229",myport); - -buf = 100000; - -TCPSock = socket(AF_INET,SOCK_STREAM); -#TCPSock = socket(AF_INET,SOCK_DGRAM); -TCPSock.bind(myaddr); -TCPSock.connect((host,port)); - -f_mhz = 2400; -f_hz = 0; -gain = 2; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman -#samples = 0xffffffff; #8-15 fft:(returns 2^number[8-15]) raw:(returns number) -samples = 2; #8-15 fft:(returns 2^number[8-15]) raw:(returns number) -decim = 2; #0-8 -#decim = decim+16; # +16 to use 16bit instead of 32 bit -mode = 1; #0=IQ, 1=MAG, 2=MAGDB -sets = 0xffffffff; -#sets = 1; - -fft_data = struct.pack("<IIIIIIIIII", 0x02, 0x20, f_mhz, f_hz, gain,window, samples, decim, mode,sets); -raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); -stat_data = struct.pack("!II", 0x0000, 0x0000) - -data = raw_data; - -#TCPSock.sendto(data, (host,port)) -TCPSock.send(data); - -print "sent" - - - -count = 0; -while(1): - data,addr = TCPSock.recvfrom(buf); - - print "got response" - - print "Data length: %d bytes."%(len(data)); - if(len(data)==12): - a,b,c = struct.unpack("!III",data); - print "%x,%x,%x"%(a,b,c); - - datavector = []; - - for d in data: - a = struct.unpack("<b",d); - datavector.append(a); - - print datavector; - - count = count + 1; - - if(count > 1): - sets = 3; - raw_data_2 = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); - TCPSock.send(raw_data_2); - - - -TCPSock.close(); - - - diff --git a/gr-msdd6000/src/python_test/test_tcp_fft.py b/gr-msdd6000/src/python_test/test_tcp_fft.py deleted file mode 100644 index b02db815d..000000000 --- a/gr-msdd6000/src/python_test/test_tcp_fft.py +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; - -myport = random.randint(1025,65535); - -port = 10000 -host = "10.45.4.43" -myaddr = ("10.45.1.229",myport); - -buf = 100000; - -TCPSock = socket(AF_INET,SOCK_STREAM); -#TCPSock = socket(AF_INET,SOCK_DGRAM); -TCPSock.bind(myaddr); -TCPSock.connect((host,port)); - -f_mhz = 2400; -f_hz = 0; -gain = 2; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman -#samples = 0xffffffff; #8-15 fft:(returns 2^number[8-15]) raw:(returns number) -samples = 2; #8-15 fft:(returns 2^number[8-15]) raw:(returns number) -decim = 2; #0-8 -#decim = decim+16; # +16 to use 16bit instead of 32 bit -mode = 1; #0=IQ, 1=MAG, 2=MAGDB -sets = 0xffffffff; -#sets = 1; - -fft_data = struct.pack("<IIIIIIIIII", 0x02, 0x20, f_mhz, f_hz, gain,window, samples, decim, mode,sets); -raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); -stat_data = struct.pack("!II", 0x0000, 0x0000) - -data = raw_data; - -#TCPSock.sendto(data, (host,port)) -TCPSock.send(data); - -print "sent" - - - -count = 0; -while(1): - data,addr = TCPSock.recvfrom(buf); - - print "got response" - - print "Data length: %d bytes."%(len(data)); - if(len(data)==12): - a,b,c = struct.unpack("!III",data); - print "%x,%x,%x"%(a,b,c); - - datavector = []; - - for d in data: - a = struct.unpack("<b",d); - datavector.append(a); - - print datavector; - - count = count + 1; - - if(count > 1): - sets = 3; - raw_data_2 = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); - TCPSock.send(raw_data_2); - - - -TCPSock.close(); - - - diff --git a/gr-msdd6000/src/python_test/test_udp.py b/gr-msdd6000/src/python_test/test_udp.py deleted file mode 100755 index fd93847e9..000000000 --- a/gr-msdd6000/src/python_test/test_udp.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; - -msdd_port = 10001 -msdd_host = "10.45.4.43" - -my_udp_addr = ("10.45.1.229",10001); - -buf = 1024; - -#myport = random.randint(1025,65535); -#my_tcp_addr = ("10.45.1.229",myport); -#TCPSock = socket(AF_INET,SOCK_STREAM); -#TCPSock.bind(my_tcp_addr); -#TCPSock.connect((msdd_host,msdd_port)); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -SETS_STREAM = 0xffffffff; - -f_mhz = 2400; -f_hz = 1; -gain = 3; -samples = 512; - -decim = 2; - -#sets = 16; -sets = SETS_STREAM; -window = 3; -mode = 1; - - -# construct the 3 different request type packets -fft_data = struct.pack("<IIIIIIIIII", 0x02, 0x20, f_mhz, f_hz, gain,window, samples, decim, mode,sets); -raw_data = struct.pack("<IIIIIIII", 0x01, 0x18, f_mhz, f_hz, gain,samples, decim,sets); -stat_data = struct.pack("!II", 0x0000, 0x0000) - -# send appropriate udp request packet -UDPSock.sendto(raw_data, (msdd_host,msdd_port)) - -#TCPSock.send(raw_data); - - -print "sent request" - - -print "waiting for response" -data,addr = UDPSock.recvfrom(buf); - -print "got response" - -print data; diff --git a/gr-msdd6000/src/python_test/udp_stream_cap.py b/gr-msdd6000/src/python_test/udp_stream_cap.py deleted file mode 100644 index 6326f27c5..000000000 --- a/gr-msdd6000/src/python_test/udp_stream_cap.py +++ /dev/null @@ -1,110 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.43" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -#f_mhz = 3500; -#f_mhz = 3500; -f_mhz = 1000; -f_hz = 0; -gain = 0; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -#samples = 65535; -samples = 16384; -#samples = samples*4; #bytes of data we are requesting - -decim = 4; #0-8 (3 => 2^3 = 8) -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - - -numtocap = 1000; -IQ_bytes = 4 * numtocap; - -numbytes = 100 * 65536; - -num_rx = 0; -start = time.time(); - -d = []; -while(num_rx < numbytes): - data = UDPSock.recv(65536); - num_rx = num_rx + len(data); - d.append(data); - -mags = []; -for i in range(0, len(d)/4): - v = struct.unpack_from("<f",d, i*4); - mags.append(abs(v)); -plot(mags); -show(); - -end = time.time(); -print "recieved %d bytes in %f sec"%(numbytes, end-start); - -bytes_per_sec = numbytes / (end-start); -samples_per_sec = bytes_per_sec / 4; -MSPS = samples_per_sec / 1000000.0; - -print "Got %f MSPS"%(MSPS); -print "Expected %f MSPS"%(102.4/math.pow(2,(1+decim-16))); - - -halt_data = struct.pack("<II", 0x04, 0x00); -UDPSock.sendto(halt_data, (msdd_host, msdd_port)); - - -UDPSock.close(); - diff --git a/gr-msdd6000/src/python_test/udp_stream_rate_test.py b/gr-msdd6000/src/python_test/udp_stream_rate_test.py deleted file mode 100644 index 0b75f2372..000000000 --- a/gr-msdd6000/src/python_test/udp_stream_rate_test.py +++ /dev/null @@ -1,106 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.46" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -#f_mhz = 3500; -#f_mhz = 3500; -f_mhz = 1000; -f_hz = 0; -gain = 0; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -#samples = 65535; -samples = 16384; -#samples = samples*4; #bytes of data we are requesting - -decim = 2; #0-8 (3 => 2^3 = 8) # ok -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - - -numtocap = 1000; -IQ_bytes = numtocap * numtocap; - -numbytes = 1000 * 65536; - -num_rx = 0; -start = -1; -while(num_rx < numbytes): - data = UDPSock.recv(65536); - - if(start==-1): - start = time.time(); - - num_rx = num_rx + len(data); -# print num_rx; - - -end = time.time(); -print "recieved %d bytes in %f sec"%(numbytes, end-start); - -bytes_per_sec = numbytes / (end-start); -samples_per_sec = bytes_per_sec / 4; -MSPS = samples_per_sec / 1000000.0; - -print "Got %f MSPS"%(MSPS); -print "Expected %f MSPS"%(102.4/math.pow(2,(decim-16))); - - -halt_data = struct.pack("<II", 0x04, 0x00); -UDPSock.sendto(halt_data, (msdd_host, msdd_port)); - - -UDPSock.close(); - diff --git a/gr-msdd6000/src/python_test/udp_stream_rate_test_plot.py b/gr-msdd6000/src/python_test/udp_stream_rate_test_plot.py deleted file mode 100644 index eef78f51b..000000000 --- a/gr-msdd6000/src/python_test/udp_stream_rate_test_plot.py +++ /dev/null @@ -1,161 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -from random import *; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.46" - -buf = 100000; - -my_udp_addr = ('',randint(1025,65535)); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -f_mhz = 2500; - -print "fc = %d"%(f_mhz); - -f_hz = 0; -gain = 20; # attenuation -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -samples = 65535*4*2; -#samples = 16384; -#samples = 16*1024*1024; -#samples = samples*4; #bytes of data we are requesting - -# decim 0-8 ( 3 - 8 ) -#decim = 5; # rate ok -decim = 8; -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - - -numtocap = 1000; -IQ_bytes = 4 * numtocap; - -numbytes = 65536*100; -#numbytes = 65536*2; -#numbytes = 1024; - -num_rx = 0; -start = time.time(); -l = []; -arr = []; - -while(num_rx < numbytes): - data = UDPSock.recv(1024); - l.append(data); - num_rx = num_rx + len(data); - - -end = time.time(); - -# send stop command -halt_data = struct.pack(">II", 0x04, 0x00); -UDPSock.sendto(halt_data, (msdd_host, msdd_port)); - -# perform timing analysis -print "recieved %d bytes in %f sec"%(numbytes, end-start); -bytes_per_sec = numbytes / (end-start); -samples_per_sec = bytes_per_sec / 4; -MSPS = samples_per_sec / 1000000.0; - -print "Got %f MSPS"%(MSPS); -print "Expected %f MSPS"%(102.4/math.pow(2,(decim-16))); - - -# plot data -val_arr = []; -mag_arr = []; -mag_arr2 = []; - -print "Repacking data..." -f = open("out.dat","w"); -for li in l: - for p in range(0, len(li)/4): - [i,q] = struct.unpack_from("<hh", li, p*4); - val = complex(i,q); - mag_arr.append((val*conj(val)).real); - val_arr.append(val); - binchunk = struct.pack("<ff",float(val.real), float(val.imag) ); - f.write(binchunk); -f.close(); - - -dlen = len(val_arr)-1; -fft_data = []; -for i in range(1, dlen-1024, 1024*1024): - - t_in = []; - for ind in range(i, i+1024): - t_in.append(val_arr[ind]); - - tmp = 20*log10(fftshift(fft(t_in))); - #tmp = (fftshift(fft(t_in))); - - if(len(fft_data) == 0): - for ind in range(0,1024): - fft_data.append( tmp[ind] ); - else: - for ind in range(0,1024): - fft_data[ind] = fft_data[ind] + tmp[ind]; - - - - -print "Plotting..." -subplot(2,1,1); -plot(mag_arr); -title("T power"); -subplot(2,1,2); -plot(10*log10(fft_data)); -title("PSD"); -show(); - - - -UDPSock.close(); - diff --git a/gr-msdd6000/src/python_test/udp_stream_rate_test_plot_loop.py b/gr-msdd6000/src/python_test/udp_stream_rate_test_plot_loop.py deleted file mode 100644 index 185afc48c..000000000 --- a/gr-msdd6000/src/python_test/udp_stream_rate_test_plot_loop.py +++ /dev/null @@ -1,150 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -#msdd_host = "10.45.4.43" -msdd_host = "10.45.4.45" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -#f_mhz = 3500; -f_mhz = 1500; -#f_mhz = 1000; -f_hz = 0; -gain = 80; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -#samples = 65535; -samples = 16384; -#samples = samples*4; #bytes of data we are requesting - -# decim 0-8 ( 3 - 8 ) -#decim = 5; # rate ok -decim = 4; -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); -start = time.time(); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - - -numtocap = 1000; -IQ_bytes = 4 * numtocap; - -#numbytes = 65536*100; -numbytes = 65536; - - - -while(True): - - data = []; - l = []; - num_rx = 0; - while(num_rx < numbytes): - data = UDPSock.recv(65536); - num_rx = num_rx + len(data); - l.append(data); - - end = time.time(); - - # send stop command - #halt_data = struct.pack("<II", 0x04, 0x00); - #UDPSock.sendto(halt_data, (msdd_host, msdd_port)); - - # perform timing analysis - print "recieved %d bytes in %f sec"%(numbytes, end-start); - bytes_per_sec = numbytes / (end-start); - samples_per_sec = bytes_per_sec / 4; - MSPS = samples_per_sec / 1000000.0; - - print "Got %f MSPS"%(MSPS); - print "Expected %f MSPS"%(102.4/math.pow(2,(decim-16))); - - - # plot data - val_arr = []; - mag_arr = []; - - print "Repacking data..." - for li in l: - for p in range(0, len(li)/4): - [i,q] = struct.unpack_from("<hh", li, p); - val = complex(i,q); - mag_arr.append(abs(val)); - val_arr.append(val); - - - print "Calculating Time Domain Power..." - tpwr = []; - for i in val_arr: - tpwr.append( (i*conj(i)).real ); - - print "Calculating PSD..." - freqz = fft(val_arr); - - #freqz = []; - # - #for i in range(0, floor(len(val_arr)/2048)): - # tmp = val_arr(range(i,i+2048)); - # if len(freqz) == 0: - # freqz = tmp; - # - - psd = (freqz * conj(freqz)).real; - - print "Plotting..." - subplot(2,1,1); - plot(tpwr); - subplot(2,1,2); - plot(10*log10(psd)); - show(); - -UDPSock.close(); - diff --git a/gr-msdd6000/src/python_test/udp_stream_test.py b/gr-msdd6000/src/python_test/udp_stream_test.py deleted file mode 100644 index 6136d16c5..000000000 --- a/gr-msdd6000/src/python_test/udp_stream_test.py +++ /dev/null @@ -1,127 +0,0 @@ -#!/usr/bin/python - -from socket import * -import string -import time -import struct; -import random; -import array; -import cmath; -from numpy import *; -from numpy.fft import *; -from pylab import *; - -myport = random.randint(1025,65535); -filename = "output.dat"; - -msdd_port = 10001 -msdd_host = "10.45.4.46" - -buf = 100000; - -my_udp_addr = ('',10001); -my_udp_addr = ('10.45.1.229 ',10001); - -UDPSock = socket(AF_INET,SOCK_DGRAM); -UDPSock.bind(my_udp_addr); - -#f_mhz = 3500; -#f_mhz = 3500; -f_mhz = 2500; -f_hz = 0; -gain = 0; -window = 3; #0=rect, 1=hanning, 2=hamming, 3=blackman - -samples = 65535; -samples = samples*4; #bytes of data we are requesting - -decim = 2; #0-8 (3 => 2^3 = 8) -decim = decim+16; # +16 to use 16bit floats instead of 32 bit floats -mode = 0; #0=IQ, 1=MAG, 2=MAGDB -#sets = 0; -sets = 0xffffffff; - -size_int = 4; -request_len = 6*size_int; # 6 int items not including the 8 bytes for opcode and length fields -print "request len = %d"%(request_len); - -raw_data = struct.pack("<IIIIIIII", 0x01, request_len, f_mhz, f_hz, gain, samples, decim, sets); - -data = raw_data; - -UDPSock.sendto(data, (msdd_host, msdd_port)); - -print "sent" - - - -count = 0; - -total_data = []; - -state = 0; - -vals = []; -mags = []; -re = []; - -sample_count = 0; -IQ_bytes=0; - - -numtocap = 1000; -IQ_bytes = 4 * numtocap; - -while(True): - data = UDPSock.recv(4); - [i,q] = struct.unpack("<hh", data); - tmp = complex(i,q); - - re.append(i); - vals.append(tmp); - mags.append(abs(tmp)); - - - sample_count = sample_count + 1; -# print "sample count %d"%(sample_count) - - IQ_bytes = IQ_bytes - 4; - if(IQ_bytes % 200 == 0): - print IQ_bytes; - if(IQ_bytes < 4): - print "got all data (total %d)"%(sample_count); - print "remaining: %d"%(IQ_bytes); - break; - - -halt_data = struct.pack("<II", 0x04, 0x00); -UDPSock.sendto(halt_data, (msdd_host, msdd_port)); - - - -UDPSock.close(); - -print "done" -nmags = [] -for i in mags: - if i == 0: - i=1; - nmags.append(i); - - -subplot(2,1,1); -plot(20*log10(nmags)); - -fft_data = 20*log10(fftshift(fft(vals))); - -subplot(2,1,2); -plot(fft_data); -show(); - -f = open(filename, "w"); -for sample in vals: - binchunk = struct.pack("<ff",float(sample.real), float(sample.imag) ); - f.write(binchunk); -f.close(); - - diff --git a/gr-msdd6000/src/qa_msdd_source_simple.py b/gr-msdd6000/src/qa_msdd_source_simple.py deleted file mode 100755 index 5262fcef0..000000000 --- a/gr-msdd6000/src/qa_msdd_source_simple.py +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/python - -from pylab import *; -#from scipy.fftpack import fftshift; - -import math; - -from gnuradio import msdd,gr; - - -tb = gr.top_block(); - - -src = msdd.source_simple("10.45.4.43",0); -convert = gr.interleaved_short_to_complex(); -sink = gr.vector_sink_c(); - -gain = 40; - -fc = 2.4e9; - -src.set_decim_rate(8); -#src.set_rx_freq(0,3500000000); -src.set_rx_freq(0,fc); -src.set_pga(0,gain); - - -tb.connect(src, convert, sink); - - -tb.start(); - -v = [] -for i in range(0,10000): - b = math.sqrt(i); - v.append(b); - -tb.stop(); - -#print sink.data(); - -data = sink.data(); - -plot(10*log10(fftshift(fft(sink.data())))); -show(); diff --git a/gr-radar-mono/.gitignore b/gr-radar-mono/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/Makefile.am b/gr-radar-mono/Makefile.am deleted file mode 100644 index 98e3daf02..000000000 --- a/gr-radar-mono/Makefile.am +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += README -SUBDIRS = src doc diff --git a/gr-radar-mono/README b/gr-radar-mono/README deleted file mode 100644 index 577c8e095..000000000 --- a/gr-radar-mono/README +++ /dev/null @@ -1,67 +0,0 @@ -This GNU Radio component implements a monostatic radar transmitter -and receiver. It uses a custom FPGA build to generate a linear -FM chirp waveform directly in the USRP. Echo returns are recorded -to a file for offline analysis. - -The LFM chirp can be up to 32 MHz in width, whose center frequency -is set by which transmit daughter board is installed. This gives -a range resolution of approximately 5 meters. - -The script to run is placed in $prefix/bin: - -Usage: usrp_radar_mono.py [options] - -Options: - -h, --help show this help message and exit - -T TX_SUBDEV_SPEC, --tx-subdev-spec=TX_SUBDEV_SPEC - use transmitter board side A or B (default is first - found) - -R RX_SUBDEV_SPEC, --rx-subdev-spec=RX_SUBDEV_SPEC - use receiver board side A or B (default is first - found) - -g GAIN, --gain=GAIN set gain in dB (default is midpoint) - -f FREQ, --frequency=FREQ - set transmitter center frequency to FREQ in Hz, - default is 0.0 - -w FREQ, --chirp-width=FREQ - set LFM chirp bandwidth in Hz, default is 32M - -a AMPLITUDE, --amplitude=AMPLITUDE - set waveform amplitude in % full scale, default is 15, - --ton=TON set pulse on period in seconds, default is 5e-06, - --tsw=TSW set transmitter switching period in seconds, default - is 4.0625e-07, - --tlook=TLOOK set receiver look time in seconds, default is 5e-06, - --prf=PRF set pulse repetition frequency in Hz, default is - 10000.0, - -v, --verbose enable verbose output, default is disabled - -D, --debug enable debugging output, default is disabled - -F FILENAME, --filename=FILENAME - log received echos to file - -The transmitter creates an LFM chirp, evenly centered on the supplied frequency. -The four timing parameters are: - -ton Chirp on time in seconds. - -tsw Transmitter switching time in seconds. This the delay after the chirp - is transmitted before the receiver is enabled. These two (tsw and ton) - parameters determine the minimum range of the radar. - -tlook The the amount of time in seconds the receiver is enabled to record - echo responses ("look" time). This parameter determines the maximum - radar range that can be measured, though transmitter power will also - limit return strength and practical range. - -prf Pulse repetition frequency in Hz. This establishes to overall pulse - repetition period, which results in idle time between when the receiver - is turned off and the next transmitted chirp begins. - -The transmitter is completed. The receive path is logging echo data to a supplied -file; however, no meta-data is logged. - -This is experimental code. - -Johnathan Corgan -Corgan Enterprises LLC -jcorgan@corganenterprises.com -9/17/2007 diff --git a/gr-radar-mono/doc/.gitignore b/gr-radar-mono/doc/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/doc/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/doc/Makefile.am b/gr-radar-mono/doc/Makefile.am deleted file mode 100644 index 77d603f55..000000000 --- a/gr-radar-mono/doc/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += registers.ods diff --git a/gr-radar-mono/doc/registers.ods b/gr-radar-mono/doc/registers.ods Binary files differdeleted file mode 100644 index 7bafe2c58..000000000 --- a/gr-radar-mono/doc/registers.ods +++ /dev/null diff --git a/gr-radar-mono/src/.gitignore b/gr-radar-mono/src/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/Makefile.am b/gr-radar-mono/src/Makefile.am deleted file mode 100644 index d546da7f8..000000000 --- a/gr-radar-mono/src/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = fpga lib -if PYTHON -SUBDIRS += python -endif diff --git a/gr-radar-mono/src/fpga/.gitignore b/gr-radar-mono/src/fpga/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/Makefile.am b/gr-radar-mono/src/fpga/Makefile.am deleted file mode 100644 index fb2a09c9c..000000000 --- a/gr-radar-mono/src/fpga/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = lib top tb models diff --git a/gr-radar-mono/src/fpga/lib/.gitignore b/gr-radar-mono/src/fpga/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am deleted file mode 100644 index e97ff1b6a..000000000 --- a/gr-radar-mono/src/fpga/lib/Makefile.am +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - radar.v \ - radar_config.vh \ - radar_control.v \ - radar_tx.v \ - radar_rx.v \ - dac_interface.v \ - fifo32_2k.v \ - cordic_nco.v - -MOSTLYCLEANFILES += *.bak diff --git a/gr-radar-mono/src/fpga/lib/cordic_nco.v b/gr-radar-mono/src/fpga/lib/cordic_nco.v deleted file mode 100644 index b9858baf8..000000000 --- a/gr-radar-mono/src/fpga/lib/cordic_nco.v +++ /dev/null @@ -1,54 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q_o); - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - - input [15:0] ampl_i; - input [31:0] freq_i; - input [31:0] phs_i; - - output [15:0] data_i_o; - output [15:0] data_q_o; - - reg [31:0] phase_reg; - wire [31:0] phase = phase_reg + phs_i; - wire [15:0] ampl; - - always @(posedge clk_i) - begin - if (rst_i | ~ena_i) - phase_reg <= 32'b0; - else if (strobe_i) - phase_reg <= phase_reg + freq_i; - end - - assign ampl = ena_i ? ampl_i : 16'b0; - - cordic tx_cordic - (.clock(clk_i),.reset(rst_i),.enable(strobe_i), - .xi(ampl),.yi(16'b0),.zi(phase[31:16]), - .xo(data_i_o),.yo(data_q_o),.zo()); - -endmodule // cordic_nco diff --git a/gr-radar-mono/src/fpga/lib/dac_interface.v b/gr-radar-mono/src/fpga/lib/dac_interface.v deleted file mode 100644 index 209aebd96..000000000 --- a/gr-radar-mono/src/fpga/lib/dac_interface.v +++ /dev/null @@ -1,60 +0,0 @@ -// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../top/config.vh"
-
-module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
- input clk_i;
- input rst_i;
- input ena_i;
- input strobe_i;
-
- input [13:0] tx_i_i;
- input [13:0] tx_q_i;
-
- output [13:0] tx_data_o;
- output tx_sync_o;
-
-`ifdef TX_RATE_MAX
- wire clk128;
- reg clk64_d;
- reg [13:0] tx_data_o;
-
- // Create a 128 MHz clock
- dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
-
- // Register the clk64 clock in the clk128 domain
- always @(posedge clk128)
- clk64_d <= clk_i;
-
- // Register the tx data in the clk128 domain
- always @(posedge clk128)
- tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
-
- assign tx_sync_o = clk64_d;
-
-
-`else // !`ifdef TX_RATE_MAX
- assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
- assign tx_sync_o = strobe_i;
-`endif // !`ifdef TX_RATE_MAX
-
-endmodule // dac_interface
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_2k.v b/gr-radar-mono/src/fpga/lib/fifo32_2k.v deleted file mode 100755 index c045b70e7..000000000 --- a/gr-radar-mono/src/fpga/lib/fifo32_2k.v +++ /dev/null @@ -1,161 +0,0 @@ -// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo
-
-// ============================================================
-// File Name: fifo32_2k.v
-// Megafunction Name(s):
-// scfifo
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo32_2k (
- clock,
- data,
- rdreq,
- sclr,
- wrreq,
- empty,
- q);
-
- input clock;
- input [31:0] data;
- input rdreq;
- input sclr;
- input wrreq;
- output empty;
- output [31:0] q;
-
- wire sub_wire0;
- wire [31:0] sub_wire1;
- wire empty = sub_wire0;
- wire [31:0] q = sub_wire1[31:0];
-
- scfifo scfifo_component (
- .rdreq (rdreq),
- .sclr (sclr),
- .clock (clock),
- .wrreq (wrreq),
- .data (data),
- .empty (sub_wire0),
- .q (sub_wire1)
- // synopsys translate_off
- ,
- .aclr (),
- .almost_empty (),
- .almost_full (),
- .full (),
- .usedw ()
- // synopsys translate_on
- );
- defparam
- scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.intended_device_family = "Cyclone",
- scfifo_component.lpm_numwords = 2048,
- scfifo_component.lpm_showahead = "OFF",
- scfifo_component.lpm_type = "scfifo",
- scfifo_component.lpm_width = 32,
- scfifo_component.lpm_widthu = 11,
- scfifo_component.overflow_checking = "OFF",
- scfifo_component.underflow_checking = "OFF",
- scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "32"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v deleted file mode 100644 index 1023d2f25..000000000 --- a/gr-radar-mono/src/fpga/lib/radar.v +++ /dev/null @@ -1,81 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../lib/radar_config.vh" - -module radar(clk_i,saddr_i,sdata_i,s_strobe_i, - tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o, - rx_adc_i_i,rx_adc_q_i, - rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o); - - // System interface - input clk_i; // Master clock @ 64 MHz - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - - // Transmit subsystem - output tx_side_o; // Transmitter slot - output tx_strobe_o; // Generate an transmitter output sample - output [13:0] tx_dac_i_o; // I channel transmitter output to DAC - output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC - output io_tx_ena_o; // Transmit/Receive switching - - // Receive subsystem - input [15:0] rx_adc_i_i; // I channel input from ADC - input [15:0] rx_adc_q_i; // Q channel input from ADC - output rx_strobe_o; // Indicates output samples ready for Rx FIFO - output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO - output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO - - // Application control - wire reset; // Master application reset - wire tx_side; // Transmitter slot - wire debug_enabled; // Enable debugging mode; - wire tx_enable; // Transmitter enable - wire rx_enable; // Receiver enable - wire tx_ctrl; // Transmitter on control - wire rx_ctrl; // Receiver on control - wire [15:0] pulse_num; // Count of pulses since tx_enabled - - // Configuration - wire [15:0] ampl; // Pulse amplitude - wire [31:0] fstart; // Chirp start frequency - wire [31:0] fincr; // Chirp per strobe frequency increment - - radar_control controller - (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i), - .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled), - .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl), - .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num), - .io_tx_ena_o(io_tx_ena_o)); - - radar_tx transmitter - ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o), - .ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr), - .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) ); - - radar_rx receiver - ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled), - .pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i), - .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) ); - -endmodule // radar diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh deleted file mode 100644 index 89a336735..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_config.vh +++ /dev/null @@ -1,41 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -`define FR_RADAR_MODE `FR_USER_0 -`define bmFR_RADAR_MODE_RESET 32'b1 << 0 -`define bmFR_RADAR_TXSIDE 32'b1 << 1 -`define bmFR_RADAR_LOOP 32'b1 << 2 -`define bmFR_RADAR_META 32'b1 << 3 -`define bmFR_RADAR_DERAMP 32'b1 << 4 -`define bmFR_RADAR_CHIRPS 32'b11 << 5 -`define bmFR_RADAR_DEBUG 32'b1 << 7 - -`define FR_RADAR_TON `FR_USER_1 -`define FR_RADAR_TSW `FR_USER_2 -`define FR_RADAR_TLOOK `FR_USER_3 -`define FR_RADAR_TIDLE `FR_USER_4 -`define FR_RADAR_AMPL `FR_USER_5 -`define FR_RADAR_FSTART `FR_USER_6 -`define FR_RADAR_FINCR `FR_USER_7 -`define FR_RADAR_ATRDEL `FR_USER_8 diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v deleted file mode 100644 index 05b78198d..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_control.v +++ /dev/null @@ -1,166 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../lib/radar_config.vh" - -module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o, - tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o, - ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o); - - // System interface - input clk_i; // Master clock @ 64 MHz - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - - // Control and configuration outputs - output reset_o; - output tx_side_o; - output dbg_o; - output tx_strobe_o; - output tx_ctrl_o; - output rx_ctrl_o; - output [15:0] ampl_o; - output [31:0] fstart_o; - output [31:0] fincr_o; - output [15:0] pulse_num_o; - output io_tx_ena_o; - - // Internal configuration - wire lp_ena; - wire md_ena; - wire dr_ena; - wire [1:0] chirps; - wire [15:0] t_on; - wire [15:0] t_sw; - wire [15:0] t_look; - wire [31:0] t_idle; - wire [31:0] atrdel; - - // Configuration from host - wire [31:0] mode; - setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(mode)); - assign reset_o = mode[0]; - assign tx_side_o = mode[1]; - assign lp_ena = mode[2]; - assign md_ena = mode[3]; - assign dr_ena = mode[4]; - assign chirps = mode[6:5]; - assign dbg_o = mode[7]; - - setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_on)); - - setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_sw)); - - setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_look)); - - setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_idle)); - - setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(ampl_o)); - - setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(fstart_o)); - - setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(fincr_o)); - - setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(atrdel)); - - // Pulse state machine - `define ST_ON 4'b0001 - `define ST_SW 4'b0010 - `define ST_LOOK 4'b0100 - `define ST_IDLE 4'b1000 - - reg [3:0] state; - reg [31:0] count; - reg [15:0] pulse_num_o; - - always @(posedge clk_i) - if (reset_o) - begin - state <= `ST_ON; - count <= 32'b0; - pulse_num_o <= 16'b0; - end - else - case (state) - `ST_ON: - if (count == {16'b0,t_on}) - begin - state <= `ST_SW; - count <= 32'b0; - pulse_num_o <= pulse_num_o + 16'b1; - end - else - count <= count + 32'b1; - - `ST_SW: - if (count == {16'b0,t_sw}) - begin - state <= `ST_LOOK; - count <= 32'b0; - end - else - count <= count + 32'b1; - - `ST_LOOK: - if (count == {16'b0,t_look}) - begin - state <= `ST_IDLE; - count <= 32'b0; - end - else - count <= count + 32'b1; - - `ST_IDLE: - if (count == t_idle) - begin - state <= `ST_ON; - count <= 32'b0; - end - else - count <= count + 32'b1; - - default: // Invalid state, reset state machine - begin - state <= `ST_ON; - count <= 32'b0; - end - endcase - - assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz - assign tx_ctrl_o = (state == `ST_ON); - assign rx_ctrl_o = (state == `ST_LOOK); - - // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch - atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o), - .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]), - .atr_tx_o(io_tx_ena_o)); - -endmodule // radar_control diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v deleted file mode 100644 index 4b0b83c49..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_rx.v +++ /dev/null @@ -1,109 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i, - rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o); - - input clk_i; - input rst_i; - input ena_i; - input dbg_i; - - input [15:0] rx_in_i_i; - input [15:0] rx_in_q_i; - input [15:0] pulse_num_i; - - output [15:0] rx_i_o; - output [15:0] rx_q_o; - output reg rx_strobe_o; - - reg [15:0] count; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - count <= 16'b0; - else - count <= count + 16'b1; - - wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i}; - - // Buffer incoming samples every clock - wire [31:0] fifo_out; - reg fifo_ack; - wire fifo_empty; - -// Use model if simulating, otherwise Altera Megacell -`ifdef SIMULATION - fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i), - .data(fifo_inp),.wrreq(ena_i), - .rdreq(fifo_ack),.q(fifo_out), - .empty(fifo_empty)); -`else - fifo32_2k buffer(.clock(clk_i),.sclr(rst_i), - .data(fifo_inp),.wrreq(ena_i), - .rdreq(fifo_ack),.q(fifo_out), - .empty(fifo_empty)); -`endif - - // Write samples to rx_fifo every third clock - `define ST_FIFO_IDLE 3'b001 - `define ST_FIFO_STROBE 3'b010 - `define ST_FIFO_ACK 3'b100 - - reg [2:0] state; - - always @(posedge clk_i) - if (rst_i) - begin - state <= `ST_FIFO_IDLE; - rx_strobe_o <= 1'b0; - fifo_ack <= 1'b0; - end - else - case (state) - `ST_FIFO_IDLE: - if (!fifo_empty) - begin - // Tell rx_fifo sample is ready - rx_strobe_o <= 1'b1; - state <= `ST_FIFO_STROBE; - end - `ST_FIFO_STROBE: - begin - rx_strobe_o <= 1'b0; - // Ack our FIFO - fifo_ack <= 1'b1; - state <= `ST_FIFO_ACK; - end - `ST_FIFO_ACK: - begin - fifo_ack <= 1'b0; - state <= `ST_FIFO_IDLE; - end - endcase // case(state) - - assign rx_i_o = fifo_out[31:16]; - assign rx_q_o = fifo_out[15:0]; - -endmodule // radar_rx diff --git a/gr-radar-mono/src/fpga/lib/radar_tx.v b/gr-radar-mono/src/fpga/lib/radar_tx.v deleted file mode 100644 index c20dd0c1a..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_tx.v +++ /dev/null @@ -1,59 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module radar_tx(clk_i,rst_i,ena_i,strobe_i, - ampl_i,fstart_i,fincr_i, - tx_i_o,tx_q_o); - - // System control - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - - // Configuration - input [15:0] ampl_i; - input [31:0] fstart_i; - input [31:0] fincr_i; - - // Chirp output - output [13:0] tx_i_o; - output [13:0] tx_q_o; - wire [15:0] cordic_i, cordic_q; - - // Chirp generator - reg [31:0] freq; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - freq <= fstart_i; - else - if (strobe_i) - freq <= freq + fincr_i; - - cordic_nco nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i), - .ampl_i(ampl_i),.freq_i(freq),.phs_i(0), - .data_i_o(cordic_i),.data_q_o(cordic_q)); - - assign tx_i_o = cordic_i[13:0]; - assign tx_q_o = cordic_q[13:0]; - -endmodule // radar_tx diff --git a/gr-radar-mono/src/fpga/models/.gitignore b/gr-radar-mono/src/fpga/models/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/models/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/models/Makefile.am b/gr-radar-mono/src/fpga/models/Makefile.am deleted file mode 100644 index 8a1a09597..000000000 --- a/gr-radar-mono/src/fpga/models/Makefile.am +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - fifo_1clk.v diff --git a/gr-radar-mono/src/fpga/models/fifo_1clk.v b/gr-radar-mono/src/fpga/models/fifo_1clk.v deleted file mode 100644 index 93ada6c8d..000000000 --- a/gr-radar-mono/src/fpga/models/fifo_1clk.v +++ /dev/null @@ -1,88 +0,0 @@ -/* -*- verilog -*- */ -/* - * Copyright (C) 2003 Matt Ettus - * Copyright (C) 2007 Corgan Enterprises LLC - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -// Model of Altera FIFO with common clock domain - -module fifo_1clk(data, wrreq, rdreq, clock, sclr, q, - full, empty, usedw); - - parameter width = 32; - parameter depth = 4096; - //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req - - input [31:0] data; - input wrreq; - input rdreq; - input clock; - input sclr; - output [31:0] q; - output full; - output empty; - output [11:0] usedw; - - reg [width-1:0] mem [0:depth-1]; - reg [7:0] rdptr; - reg [7:0] wrptr; - -`ifdef rd_req - reg [width-1:0] q; -`else - wire [width-1:0] q; -`endif - - reg [11:0] usedw; - - integer i; - - always @( sclr) - begin - wrptr <= #1 0; - rdptr <= #1 0; - for(i=0;i<depth;i=i+1) - mem[i] <= #1 0; - end - - always @(posedge clock) - if(wrreq) - begin - wrptr <= #1 wrptr+1; - mem[wrptr] <= #1 data; - end - - always @(posedge clock) - if(rdreq) - begin - rdptr <= #1 rdptr+1; -`ifdef rd_req - q <= #1 mem[rdptr]; -`endif - end - -`ifdef rd_req -`else - assign q = mem[rdptr]; -`endif - - always @(posedge clock) - usedw <= #1 wrptr - rdptr; - - assign empty = (wrptr == rdptr); -endmodule diff --git a/gr-radar-mono/src/fpga/tb/.gitignore b/gr-radar-mono/src/fpga/tb/.gitignore deleted file mode 100644 index d709d8c29..000000000 --- a/gr-radar-mono/src/fpga/tb/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -/Makefile -/Makefile.in -/radar_tb -/out -/*.out* -/*.vcd diff --git a/gr-radar-mono/src/fpga/tb/Makefile.am b/gr-radar-mono/src/fpga/tb/Makefile.am deleted file mode 100644 index da45f497a..000000000 --- a/gr-radar-mono/src/fpga/tb/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - radar_tb.v \ - radar_tb.sav \ - radar_tb.sh \ - radar_tb_wave.sh - -MOSTLYCLEANFILES += *.vcd *.out* radar_tb diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sav b/gr-radar-mono/src/fpga/tb/radar_tb.sav deleted file mode 100644 index 66289c07e..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.sav +++ /dev/null @@ -1,42 +0,0 @@ -*-24.712532 40200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -radar_tb.clk -radar_tb.ena -radar_tb.rst -radar_tb.uut.reset -@200 -- -@420 -radar_tb.uut.controller.ampl_o[15:0] -@22 -radar_tb.uut.controller.fstart_o[31:0] -radar_tb.uut.controller.fincr_o[31:0] -radar_tb.uut.transmitter.freq[31:0] -@200 -- -@28 -radar_tb.tx_strobe -@8420 -radar_tb.uut.tx_dac_i_o[13:0] -@8421 -radar_tb.uut.tx_dac_q_o[13:0] -@200 -- -@28 -radar_tb.uut.io_tx_ena_o -radar_tb.uut.controller.tx_ctrl_o -radar_tb.uut.controller.rx_ctrl_o -@200 -- -@28 -radar_tb.fifo_strobe -@8024 -radar_tb.fifo_i[15:0] -@22 -radar_tb.fifo_q[15:0] -@200 -- -@22 -radar_tb.uut.pulse_num[15:0] -@200 -- diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sh b/gr-radar-mono/src/fpga/tb/radar_tb.sh deleted file mode 100755 index dabbe6754..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh -iverilog \ - -D SIMULATION \ - -y ../lib/ \ - -y ../../../../usrp/fpga/sdr_lib \ - -y ../models/ \ - radar_tb.v -o radar_tb && ./radar_tb > radar_tb.out diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.v b/gr-radar-mono/src/fpga/tb/radar_tb.v deleted file mode 100644 index 3583b70e9..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.v +++ /dev/null @@ -1,215 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`timescale 1ns/1ps - -`include "../lib/radar.v" - -module radar_tb; - - // System bus - reg clk; - reg rst; - reg ena; - - // Configuration bus - reg [6:0] saddr; - reg [31:0] sdata; - reg s_strobe; - - // DAC bus - wire tx_strobe; - wire [13:0] tx_dac_i; - wire [13:0] tx_dac_q; - - // ADC bus - reg [15:0] rx_adc_i; - reg [15:0] rx_adc_q; - - // FIFO bus - wire fifo_strobe; - wire [15:0] fifo_i; - wire [15:0] fifo_q; - - // Configuration shadow registers - reg [31:0] mode; - - radar uut - (.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe), - .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q), - .rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q), - .rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q)); - - // Start up initialization - initial - begin - clk = 0; - rst = 0; - ena = 0; - saddr = 0; - sdata = 0; - s_strobe = 0; - rx_adc_i = 0; - rx_adc_q = 0; - mode = 0; - - @(posedge clk); - rst = 1; - @(posedge clk); - rst = 0; - @(posedge clk); - ena = 1; - end - - always - #5 clk <= ~clk; - - initial - begin - //$monitor($time, " clk=%b rst=%b", clk, uut.reset); - - $dumpfile("radar_tb.vcd"); - $dumpvars(0, radar_tb); - end - - // Test tasks - task write_cfg_register; - input [6:0] regno; - input [31:0] value; - - begin - @(posedge clk); - saddr <= regno; - sdata <= value; - s_strobe <= 1'b1; - @(posedge clk); - s_strobe <= 0; - end - endtask // write_cfg_register - - // Application reset line - task set_reset; - input reset; - - begin - mode = reset ? (mode | `bmFR_RADAR_MODE_RESET) : (mode & ~`bmFR_RADAR_MODE_RESET); - write_cfg_register(`FR_RADAR_MODE, mode); - end - endtask // reset - - // Waveform on time - task set_ton; - input [23:0] t_on; - - begin - write_cfg_register(`FR_RADAR_TON, t_on); - end - endtask // set_ton - - // Transmitter switching time - task set_tsw; - input [23:0] t_sw; - - begin - write_cfg_register(`FR_RADAR_TSW, t_sw); - end - endtask // t_sw - - // Receiver look time - task set_tlook; - input [23:0] t_look; - - begin - write_cfg_register(`FR_RADAR_TLOOK, t_look); - end - endtask // set_tlook - - // Inter-pulse idle time - task set_tidle; - input [23:0] t_idle; - - begin - write_cfg_register(`FR_RADAR_TIDLE, t_idle); - end - endtask // set_tidle - - // Chirp amplitude - task set_ampl; - input [31:0] ampl; - - begin - write_cfg_register(`FR_RADAR_AMPL, ampl); - end - endtask // set_ampl - - // Chirp start frequency - task set_fstart; - input [31:0] fstart; - - begin - write_cfg_register(`FR_RADAR_FSTART, fstart); - end - endtask // set_fstart - - // Chirp frequency increment - task set_fincr; - input [31:0] fincr; - - begin - write_cfg_register(`FR_RADAR_FINCR, fincr); - end - endtask // set_fincr - - // Chirp frequency increment - task set_atrdel; - input [31:0] atrdel; - - begin - write_cfg_register(`FR_RADAR_ATRDEL, atrdel); - end - endtask // set_fincr - - // Test transmitter functionality - task test_tx; - begin - #20 set_reset(1); - - #20 set_ton(320-1); // 5us on time - #20 set_tsw(26-1); // 406ns switching time - #20 set_tlook(640-1); // 10us look time - #20 set_tidle(2854-1); // 60us pulse period - - #20 set_ampl(16'd9946); - #20 set_fstart(32'h80000000); // -16 to 16 MHz - #20 set_fincr (32'h0199999A); - #20 set_atrdel(32'h00400046); // 64 TX clks, 70 RX clks - #20 set_reset(0); - #200000; - end - endtask // test_tx - - // Execute tests - initial - begin - #20 test_tx; - #100 $finish; - end -endmodule diff --git a/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh b/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh deleted file mode 100755 index 45bba9f5e..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -gtkwave radar_tb.vcd radar_tb.sav diff --git a/gr-radar-mono/src/fpga/top/.gitignore b/gr-radar-mono/src/fpga/top/.gitignore deleted file mode 100644 index 40492321d..000000000 --- a/gr-radar-mono/src/fpga/top/.gitignore +++ /dev/null @@ -1,21 +0,0 @@ -/*.qmsg -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.rbf -/*.smsg -/*.sof -/*.ttf -/*.summary -/undo_redo.txt -/db -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/top/Makefile.am b/gr-radar-mono/src/fpga/top/Makefile.am deleted file mode 100644 index 51f73ebfe..000000000 --- a/gr-radar-mono/src/fpga/top/Makefile.am +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -RBFS = usrp_radar_mono.rbf - -rbf2datadir = $(prefix)/share/usrp/rev2 -dist_rbf2data_DATA = $(RBFS) - -rbf4datadir = $(prefix)/share/usrp/rev4 -dist_rbf4data_DATA = $(RBFS) - -EXTRA_DIST += \ - usrp_radar_mono.csf \ - usrp_radar_mono.esf \ - usrp_radar_mono.psf \ - usrp_radar_mono.qpf \ - usrp_radar_mono.qsf \ - usrp_radar_mono.v - -MOSTLYCLEANFILES += \ - db/* \ - *.rpt \ - *.summary \ - *.qws \ - *.smsg \ - *.done \ - *.pin \ - *.sof diff --git a/gr-radar-mono/src/fpga/top/config.vh b/gr-radar-mono/src/fpga/top/config.vh deleted file mode 100644 index 176979412..000000000 --- a/gr-radar-mono/src/fpga/top/config.vh +++ /dev/null @@ -1,24 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz -//`define TX_RATE_MAX - diff --git a/gr-radar-mono/src/fpga/top/dacpll.v b/gr-radar-mono/src/fpga/top/dacpll.v deleted file mode 100644 index f3941bc67..000000000 --- a/gr-radar-mono/src/fpga/top/dacpll.v +++ /dev/null @@ -1,291 +0,0 @@ -// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: dacpll.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.0 Build 33 02/05/2007 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module dacpll (
- areset,
- inclk0,
- c0);
-
- input areset;
- input inclk0;
- output c0;
-
- wire [5:0] sub_wire0;
- wire [0:0] sub_wire4 = 1'h0;
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire sub_wire2 = inclk0;
- wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
- altpll altpll_component (
- .inclk (sub_wire3),
- .areset (areset),
- .clk (sub_wire0),
- .activeclock (),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b1),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbout (),
- .locked (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.clk0_divide_by = 1,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 2,
- altpll_component.clk0_phase_shift = "0000",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 15625,
- altpll_component.intended_device_family = "Cyclone",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_USED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_UNUSED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf deleted file mode 100644 index 121b15aaf..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_radar_mono; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_radar_mono) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf deleted file mode 100644 index 6a8aaae42..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_radar_mono; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf deleted file mode 100644 index 064967399..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_radar_mono) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_radar_mono) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>"; - EDA_SIMULATION_TOOL = "<NONE>"; - EDA_TIMING_ANALYSIS_TOOL = "<NONE>"; - EDA_BOARD_DESIGN_TOOL = "<NONE>"; - EDA_FORMAL_VERIFICATION_TOOL = "<NONE>"; - EDA_RESYNTHESIS_TOOL = "<NONE>"; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf deleted file mode 100644 index d85239e99..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_radar_mono" diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf deleted file mode 100644 index 9b13989c2..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf +++ /dev/null @@ -1,402 +0,0 @@ -# Copyright (C) 1991-2007 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# usrp_radar_mono_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" -set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Classic Timing Assignments -# ========================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -set_global_assignment -name MAX_SCC_SIZE 50 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON -set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "<None>" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF -set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102" -set_global_assignment -name DISABLE_DA_RULE H101 - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# start CLOCK(SCLK) -# ----------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# start CLOCK(master_clk) -# ----------------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# start CLOCK(usbclk) -# ------------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ----------------------------- -# start ENTITY(usrp_radar_mono) - - # Classic Timing Assignments - # ========================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(usrp_radar_mono) -# --------------------------- -set_global_assignment -name VERILOG_FILE usrp_radar_mono.v -set_global_assignment -name VERILOG_FILE dacpll.v -set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v -set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v -set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v -set_global_assignment -name VERILOG_FILE ../lib/radar_control.v -set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v -set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v -set_global_assignment -name VERILOG_FILE ../lib/radar.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf Binary files differdeleted file mode 100644 index ee8859b1b..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf +++ /dev/null diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf deleted file mode 100644 index e5645322b..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf +++ /dev/null @@ -1,65 +0,0 @@ -{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" { } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a signal of width 4. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage11\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage10\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage9\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage8\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage7\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage6\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage5\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage4\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage3\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage2\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage1\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage0\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 81 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 75 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 72 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is connected to a signal of width 11. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a signal of width 20. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a signal of width 4. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND " "Warning: Reduced register \"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin \"MYSTERY_SIGNAL\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin \"usbrdy\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "usbctl\[0\] " "Warning: No output dependent on input pin \"usbctl\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 48 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info: Pin MYSTERY_SIGNAL has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3 has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 79 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 73 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 67 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): truncated value with size 32 to match size of target (12)" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): truncated value with size 32 to match size of target (12)" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at serial_io.v(48): object \"write_done\" assigned a value but never read" { } { { "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v deleted file mode 100644 index 2620a3288..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v +++ /dev/null @@ -1,213 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module usrp_radar_mono -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64; - - // wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_pkt_rdy; - assign usbrdy[0] = 1'b0; // have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = 1'b0; // tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] rx_numchan; - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - // TX - wire tx_sample_strobe; - wire io_tx_ena; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side - - wire tx_side; - wire [13:0] tx_i, tx_q; - wire [13:0] tx_dac; - wire tx_sync; - - dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx), - .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q), - .tx_data_o(tx_dac),.tx_sync_o(tx_sync)); - - // Route transmitted signal to side A or side B - assign tx_a = tx_side ? 14'b0 : tx_dac; - assign tx_b = tx_side ? tx_dac : 14'b0; - assign TXSYNC_A = tx_side ? 1'b0 : tx_sync; - assign TXSYNC_B = tx_side ? tx_sync : 1'b0; - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side - wire rx_strobe; - wire [15:0] rx_adc0_i, rx_adc0_q; - wire [15:0] rx_buf_i, rx_buf_q; - - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(), - .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q), - .ddc1_in_i(),.ddc1_in_q(), - .ddc2_in_i(),.ddc2_in_q(), - .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(rx_buf_i),.ch_1(rx_buf_q), - .ch_2(),.ch_3(), - .ch_4(),.ch_5(), - .ch_6(),.ch_7(), - .rxclk(clk64),.rxstrobe(rx_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus() ); - - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Top level application - radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe), - .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q), - .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q), - .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.io_tx_ena_o(io_tx_ena) - ); - - // Route TX enable out to RFX transmit mixer enable - assign io_tx_a[5] = tx_side ? 1'bz : io_tx_ena; - assign io_tx_b[5] = tx_side ? io_tx_ena : 1'bz; - - // Route opposite of TX enable out to RFX receive mixer - //assign io_rx_a[5] = tx_side ? 1'bz : ~io_tx_ena; - //assign io_rx_b[5] = tx_side ? ~io_tx_ena : 1'bz; - assign io_rx_a[5] = 1'b1; - assign io_rx_b[5] = 1'b1; - - - // Route TX enable out to RX/TX switch - assign io_tx_a[6] = tx_side ? 1'bz : ~io_tx_ena; - assign io_tx_b[6] = tx_side ? ~io_tx_ena : 1'bz; - - // Enable common RX/TX antenna - assign io_rx_a[6] = tx_side ? 1'bz : 1'b0; - assign io_rx_b[6] = tx_side ? 1'b0 : 1'bz; - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = 0; // `TX_CAP_HB; - assign capabilities[6:4] = 1; // `TX_CAP_NCHAN; - assign capabilities[3] = 0; // `RX_CAP_HB; - assign capabilities[2:0] = 2; // `RX_CAP_NCHAN; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(),.readback_5(),.readback_6(),.readback_7() - ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(),.decim_rate(), - .tx_sample_strobe(),.strobe_interp(), - .rx_sample_strobe(),.strobe_decim(), - .tx_empty(), - .debug_0(),.debug_1(), - .debug_2(),.debug_3(), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - wire [1:0] dummy_io = 2'bz; - - io_pins io_pins - (.io_0({io_tx_a[15:7],dummy_io,io_tx_a[4:0]}), // Don't connect pins used above - .io_1({io_rx_a[15:7],dummy_io,io_rx_a[4:0]}), - .io_2({io_tx_b[15:7],dummy_io,io_tx_b[4:0]}), - .io_3({io_rx_b[15:7],dummy_io,io_rx_b[4:0]}), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - -endmodule // usrp_radar_mono diff --git a/gr-radar-mono/src/lib/.gitignore b/gr-radar-mono/src/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/lib/Makefile.am b/gr-radar-mono/src/lib/Makefile.am deleted file mode 100644 index 4f35e3aef..000000000 --- a/gr-radar-mono/src/lib/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common diff --git a/gr-radar-mono/src/python/.gitignore b/gr-radar-mono/src/python/.gitignore deleted file mode 100644 index f104c5892..000000000 --- a/gr-radar-mono/src/python/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/Makefile -/Makefile.in -/run_tests -/*.pyc diff --git a/gr-radar-mono/src/python/Makefile.am b/gr-radar-mono/src/python/Makefile.am deleted file mode 100644 index 535bb85a4..000000000 --- a/gr-radar-mono/src/python/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -radar_mono_pythondir = $(grpythondir) - -dist_bin_SCRIPTS = \ - usrp_radar_mono.py - -radar_mono_python_PYTHON = \ - radar_mono.py diff --git a/gr-radar-mono/src/python/qa_nothing.py b/gr-radar-mono/src/python/qa_nothing.py deleted file mode 100644 index e69de29bb..000000000 --- a/gr-radar-mono/src/python/qa_nothing.py +++ /dev/null diff --git a/gr-radar-mono/src/python/radar_mono.py b/gr-radar-mono/src/python/radar_mono.py deleted file mode 100644 index 1a7b9260a..000000000 --- a/gr-radar-mono/src/python/radar_mono.py +++ /dev/null @@ -1,330 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, usrp -from gnuradio import eng_notation -from gr import gr_threading as _threading - -n2s = eng_notation.num_to_str - -txp_delay = 60 # Pipeline delay to turn on transmit mixer -rxp_delay = 76 # Pipeline delay to turn off transmit mixer - -#----------------------------------------------------------------------- -# FPGA Register Definitions -#----------------------------------------------------------------------- -FR_RADAR_MODE = usrp.FR_USER_0 # Operational mode -bmFR_RADAR_MODE_RESET = 1 << 0 # bit 0: active high reset -bmFR_RADAR_TXSIDE = 1 << 1 # bit 1: use TX side A or B -#bmFR_RADAR_MODE_LP = 1 << 2 # bit 2: enable digital loopback -#bmFR_RADAR_MODE_DR = 1 << 3 # bit 3: enable on-board deramping -#bmFR_RADAR_MODE_MD = 1 << 4 # bit 4: enable echo metadata -#bmFR_RADAR_MODE_CHIRPS = 3 << 5 # bit 5,6: number of chirp center frequencies -bmFR_RADAR_DEBUG = 1 << 7 # bit 7: enable debugging mode - -FR_RADAR_TON = usrp.FR_USER_1 # 16-bit transmitter on time in clocks -FR_RADAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in clocks -FR_RADAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks -FR_RADAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time -FR_RADAR_AMPL = usrp.FR_USER_5 # 16-bit pulse amplitude (2s complement) into CORDIC -FR_RADAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency -FR_RADAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit clock -FR_RADAR_ATRDEL = usrp.FR_USER_8 # 16-bit TX delay in clocks, 16-bit RX delay in clocks - -# These are for phase II development (need to renumber) -#FR_RADAR_FREQ1N = usrp.FR_USER_8 # 24-bit N register for chirp #1 -#FR_RADAR_FREQ1R = usrp.FR_USER_9 # 24-bit R register for chirp #1 -#FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit C register for chirp #1 -#FR_RADAR_FREQ2N = usrp.FR_USER_11 # 24-bit N register for chirp #2 -#FR_RADAR_FREQ2R = usrp.FR_USER_12 # 24-bit R register for chirp #2 -#FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit C register for chirp #2 -#FR_RADAR_FREQ3N = usrp.FR_USER_14 # 24-bit N register for chirp #3 -#FR_RADAR_FREQ3R = usrp.FR_USER_15 # 24-bit R register for chirp #3 -#FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit C register for chirp #3 -#FR_RADAR_FREQ4N = usrp.FR_USER_17 # 24-bit N register for chirp #4 -#FR_RADAR_FREQ4R = usrp.FR_USER_18 # 24-bit R register for chirp #4 -#FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit C register for chirp #4 - -#----------------------------------------------------------------------- -# Transmitter object. Uses usrp_sink, but only for a handle to the -# FPGA registers. -#----------------------------------------------------------------------- -class radar_tx(object): - def __init__(self, options): - self._subdev_spec = options.tx_subdev_spec - self._verbose = options.verbose - self._debug = options.debug - self._u = usrp.sink_s(fpga_filename='usrp_radar_mono.rbf') - - if self._subdev_spec == None: - self._subdev_spec = usrp.pick_tx_subdevice(self._u) - - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - self._subdev.set_lo_offset(0.0) - self._ton_ticks = 0 - self._tsw_ticks = 0 - self._tlook_ticks = 0 - self._tidle_ticks = 0 - - if self._verbose: - print "Using", self._subdev.name(), "for radar transmitter." - - def set_ton(self, ton): - self._ton_ticks = 2*(int(ton*64e6)/2)-1 # Even number, then subtract 1 - if self._verbose: - print "Setting pulse on time to", ton, " sec ("+`self._ton_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TON, self._ton_ticks) - - def set_tsw(self, tsw): - self._tsw_ticks = 2*(int(tsw*64e6)/2)-1+rxp_delay # Even number, then subtract 1 - if self._verbose: - print "Setting pulse switching time to", tsw, " sec ("+`self._tsw_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TSW, self._tsw_ticks) - - def set_tlook(self, tlook): - self._tlook_ticks = 2*(int(tlook*64e6)/2)-1 # Even number, then subtract 1 - if self._verbose: - print "Setting receiver look time to", tlook, " sec ("+`self._tlook_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TLOOK, self._tlook_ticks) - - def set_prf(self, prf): - period = 2*int(32e6/prf) - self._tidle_ticks = period-(self._ton_ticks+self._tsw_ticks+self._tlook_ticks+3)-1 - if self._verbose: - print "Setting PRF to", prf, "Hz ("+`self._tidle_ticks+1`+" ticks idle time)" - self._u._write_fpga_reg(FR_RADAR_TIDLE, self._tidle_ticks) - - def set_amplitude(self, ampl): - self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction - self._u._write_fpga_reg(FR_RADAR_AMPL, self._amplitude) - - def set_freq(self, center_freq, chirp_width): - self._center_freq = center_freq - self._chirp_width = chirp_width - self._fstart = -int((chirp_width/2)*(2**32)/32e6) - self._fincr = int((chirp_width/16e6)*(2**32)/(self._ton_ticks+1)) - - if self._verbose: - print "Setting transmitter center frequency to", n2s(center_freq) - print "Setting chirp width to", n2s(chirp_width), "Hz "+"("+hex(self._fstart)+", "+hex(self._fincr)+")" - - result = self._u.tune(0, self._subdev, center_freq) - if result == False: - raise RuntimeError("Failed to set transmitter frequency.") - self._u._write_fpga_reg(FR_RADAR_FSTART, self._fstart) - self._u._write_fpga_reg(FR_RADAR_FINCR, self._fincr) - - def start(self): - self._u.start() - self._subdev.set_enable(True) - - def stop(self): - self._subdev.set_enable(False) - self._u.stop() - - def subdev_spec(self): - return self._subdev_spec - - def echo_length(self): - return self._tlook_ticks+1 - - def __del__(self): - del self._subdev # Avoid weak reference error - -#----------------------------------------------------------------------- -# Receiver object. Uses usrp_source_c to receive echo records. -#----------------------------------------------------------------------- -class radar_rx(gr.top_block): - def __init__(self, options, callback): - gr.top_block.__init__(self, "radar_rx") - - self._u = None - self._subdev_spec = options.rx_subdev_spec - self._gain = options.gain - self._verbose = options.verbose - self._debug = options.debug - self._callback = callback - self._length_set = False - self._connected = False - self._frequency = 0.0 - self._msgq = gr.msg_queue() - self._watcher = _queue_watcher_thread(self._msgq, self._callback) - - def set_echo_length(self, length): - # Only call once - if self._length_set is True: - raise RuntimeError("Can only set echo length once.") - self._length = length - self._length_set = True - - def tune(self, frequency): - if self._verbose: - print "Setting receiver frequency to", n2s(frequency) - self._frequency = frequency - if (self._u): - result = self._u.tune(0, self._subdev, frequency) - if result == False: - raise RuntimeError("Failed to set receiver frequency.") - - def set_gain(self, gain): - self._gain = gain - if self._gain == None: - # if no gain was specified, use the mid-point in dB - g = self._subdev.gain_range() - self._gain = float(g[0]+g[1])/2 - self._subdev.set_gain(self._gain) - - def begin(self): - if not self._connected: - self._setup_connections() - - if self._verbose: - print "Starting receiver..." - self.start() - - def end(self): - if self._verbose: - print "Stopping receiver..." - self.stop() - self.wait() - if self._verbose: - print "Receiver stopped." - - def _setup_usrp(self): - self._u = usrp.source_c(fpga_filename='usrp_radar_mono.rbf') - if self._subdev_spec == None: - self._subdev_spec = usrp.pick_rx_subdevice(self._u) - self._u.set_mux(usrp.determine_rx_mux_value(self._u, self._subdev_spec)) - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - - if self._verbose: - print "Using", self._subdev.side_and_name(), "for radar receiver." - print "Setting receiver gain to", self._gain - self.set_gain(self._gain) - self.tune(self._frequency) - - def _setup_connections(self): - if not self._length_set: - raise RuntimeError("Echo length not set.") - self._setup_usrp() - self._vblen = gr.sizeof_gr_complex*self._length - self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length) - self._sink = gr.message_sink(self._vblen, self._msgq, False) - self.connect(self._u, self._s2v, self._sink) - - if self._verbose: - print "Generating echo vectors of length", self._length, \ - "(samples)", self._vblen, "(bytes)" - - self._connected = True - -class radar(object): - def __init__(self, options, callback): - - self._verbose = options.verbose - self._debug = options.debug - - self._mode = 0 - self._trans = radar_tx(options) - self._rcvr = radar_rx(options, callback) - self.set_reset(True) - self.set_tx_board(self._trans.subdev_spec()) - self.set_debug(self._debug) - self.set_atrdel() - - def _write_mode(self): - self._trans._u._write_fpga_reg(FR_RADAR_MODE, self._mode) - - def set_reset(self, value): - if value: - self._mode |= bmFR_RADAR_MODE_RESET - else: - self._mode &= ~bmFR_RADAR_MODE_RESET - self._write_mode() - - def set_tx_board(self, tx_subdev_spec): - if tx_subdev_spec[0] == 1: - self._mode |= bmFR_RADAR_TXSIDE - else: - self._mode &= ~bmFR_RADAR_TXSIDE - self._write_mode() - - def set_debug(self, value): - if value: - self._mode |= bmFR_RADAR_DEBUG - else: - self._mode &= ~bmFR_RADAR_DEBUG - self._write_mode() - - def set_ton(self, ton): - self._trans.set_ton(ton) - - def set_tsw(self, tsw): - self._trans.set_tsw(tsw) - - def set_tlook(self, tlook): - self._trans.set_tlook(tlook) - self._rcvr.set_echo_length(self._trans.echo_length()) - - def set_prf(self, prf): - self._trans.set_prf(prf) - - def set_amplitude(self, ampl): - self._trans.set_amplitude(ampl) - - def set_freq(self, center_freq, chirp_width): - self._trans.set_freq(center_freq, chirp_width) - self._rcvr.tune(center_freq) - - def set_atrdel(self, tx_delay=txp_delay, rx_delay=rxp_delay): - if self._verbose: - print "Setting TX delay of", tx_delay, "clocks, RX delay of", rx_delay - self._trans._u._write_fpga_reg(FR_RADAR_ATRDEL, tx_delay << 16 | rx_delay) - - def start(self): - self.set_reset(False) - self._trans.start() - self._rcvr.begin() - - def stop(self): - self._rcvr.end() - self._trans.stop() - self.set_reset(True) - -#----------------------------------------------------------------------- -# Queue watcher. Dispatches received echos to callback. -#----------------------------------------------------------------------- -class _queue_watcher_thread(_threading.Thread): - def __init__(self, msgq, callback): - _threading.Thread.__init__(self) - self.setDaemon(1) - self._msgq = msgq - self._callback = callback - self._keep_running = True - self.start() - - def run(self): - while self._keep_running == True: - msg = self._msgq.delete_head() - if self._callback: - self._callback(msg.to_string()) - diff --git a/gr-radar-mono/src/python/run_tests.in b/gr-radar-mono/src/python/run_tests.in deleted file mode 100644 index 19b6b895c..000000000 --- a/gr-radar-mono/src/python/run_tests.in +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -# 1st parameter is absolute path to component source directory -# 2nd parameter is absolute path to component build directory -# 3rd parameter is path to Python QA directory - -@top_builddir@/run_tests.sh \ - @abs_top_srcdir@/gr-sar-fe \ - @abs_top_builddir@/gr-sar-fe \ - @srcdir@ diff --git a/gr-radar-mono/src/python/usrp_radar_mono.py b/gr-radar-mono/src/python/usrp_radar_mono.py deleted file mode 100755 index 3f2ad28e2..000000000 --- a/gr-radar-mono/src/python/usrp_radar_mono.py +++ /dev/null @@ -1,96 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr -from gnuradio.radar_mono import radar -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import sys, time - -n2s = eng_notation.num_to_str -logfile = None - -def process_echo(echo): - global logfile - if logfile is not None: - logfile.write(echo) - -def main(): - global logfile - parser = OptionParser(option_class=eng_option) - parser.add_option("-T", "--tx-subdev-spec", type="subdev", default=None, - help="use transmitter board side A or B (default is first found)") - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="use receiver board side A or B (default is first found)") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-f", "--frequency", type="eng_float", default=0.0, - help="set transmitter center frequency to FREQ in Hz, default is %default", metavar="FREQ") - parser.add_option("-w", "--chirp-width", type="eng_float", default=32e6, - help="set LFM chirp bandwidth in Hz, default is %default", metavar="FREQ") - parser.add_option("-a", "--amplitude", type="eng_float", default=15, - help="set waveform amplitude in % full scale, default is %default,") - parser.add_option("", "--ton", type="eng_float", default=5e-6, - help="set pulse on period in seconds, default is %default,") - parser.add_option("", "--tsw", type="eng_float", default=0.0, - help="set transmitter switching period in seconds, default is %default,") - parser.add_option("", "--tlook", type="eng_float", default=5e-6, - help="set receiver look time in seconds, default is %default,") - parser.add_option("", "--prf", type="eng_float", default=100, - help="set pulse repetition frequency in Hz, default is %default,") - parser.add_option("-v", "--verbose", action="store_true", default=False, - help="enable verbose output, default is disabled") - parser.add_option("-D", "--debug", action="store_true", default=False, - help="enable debugging output, default is disabled") - parser.add_option("-F", "--filename", default=None, - help="log received echos to file") - - (options, args) = parser.parse_args() - - if len(args) != 0: - parser.print_help() - sys.exit(1) - - if options.filename is not None: - if options.verbose: - print "Logging echo records to file: ", options.filename - logfile = open(options.filename, 'wb') - - r = radar(options, process_echo) - - r.set_ton(options.ton) - r.set_tsw(options.tsw) - r.set_tlook(options.tlook) - r.set_prf(options.prf) - r.set_amplitude(options.amplitude) - r.set_freq(options.frequency, options.chirp_width) - - r.start() - raw_input("Press ENTER to stop.") - r.stop() - - if logfile is not None: - logfile.close() - -if __name__ == "__main__": - main() diff --git a/gr-radar-mono/src/utils/calc_avg.m b/gr-radar-mono/src/utils/calc_avg.m deleted file mode 100644 index b240d245e..000000000 --- a/gr-radar-mono/src/utils/calc_avg.m +++ /dev/null @@ -1,8 +0,0 @@ -function avg = calc_avg(rlen, mintime) - avg = read_avg('echos.dat', rlen); - x = 1:rlen; - x = (x/64e6+mintime)*3e8/2; - plot(x, abs(avg), "^;Amplitude;"); - xlabel("Range (meters)"); - axis([max(x) 0]) -endfunction diff --git a/gr-radar-mono/src/utils/czpad.m b/gr-radar-mono/src/utils/czpad.m deleted file mode 100644 index e2131030d..000000000 --- a/gr-radar-mono/src/utils/czpad.m +++ /dev/null @@ -1,8 +0,0 @@ -# Center and zero pad v to length n -function pad = czpad(v, n) - c = n/2; - l = length(v); - pad(c-l/2+1:c+l/2) = v; - pad(c+l/2+1:n) = 0; -endfunction -
\ No newline at end of file diff --git a/gr-radar-mono/src/utils/echo_image.m b/gr-radar-mono/src/utils/echo_image.m deleted file mode 100644 index 2e066aef5..000000000 --- a/gr-radar-mono/src/utils/echo_image.m +++ /dev/null @@ -1,6 +0,0 @@ -function echo_image(filename, data) - d = abs(data); - d = d-min(min(d)); - d = d/(max(max(d)))*255; - pngwrite(filename, d, d, d, ones(size(d))); -endfunction
\ No newline at end of file diff --git a/gr-radar-mono/src/utils/fftcorr.m b/gr-radar-mono/src/utils/fftcorr.m deleted file mode 100644 index 548988973..000000000 --- a/gr-radar-mono/src/utils/fftcorr.m +++ /dev/null @@ -1,4 +0,0 @@ -# Perform circular correlation via FFT -function corr = fftcorr(v,ref) - corr = ifft(conj(fft(ref)).*fft(v)); -endfunction diff --git a/gr-radar-mono/src/utils/pulse b/gr-radar-mono/src/utils/pulse deleted file mode 100644 index 887558d1e..000000000 --- a/gr-radar-mono/src/utils/pulse +++ /dev/null @@ -1,396 +0,0 @@ -# Created by Octave 2.1.73, Tue Sep 25 14:17:22 2007 EDT <jcorgan@mobile> -# name: __nargin__ -# type: scalar -0 -# name: pulse321 -# type: complex matrix -# rows: 64 -# columns: 1 - (-0.0003662109375,0.9998779296875) - (-0.0003662109375,0.9998779296875) - (0,-0.9996337890625) - (0,-0.9996337890625) - (-0.0010986328125,-0.961181640625) - (-0.0010986328125,-0.961181640625) - (0.0072021484375,0.882568359375) - (0.0072021484375,0.882568359375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.0765380859375,0.616943359375) - (0.0765380859375,0.616943359375) - (-0.1688232421875,-0.4447021484375) - (-0.1688232421875,-0.4447021484375) - (0.3212890625,0.26611328125) - (0.3212890625,0.26611328125) - (-0.54638671875,-0.1092529296875) - (-0.54638671875,-0.1092529296875) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.8046875,-0.019775390625) - (0.8046875,-0.019775390625) - (-0.444580078125,0.1688232421875) - (-0.444580078125,0.1688232421875) - (0.147705078125,-0.477294921875) - (0.147705078125,-0.477294921875) - (-0.0032958984375,0.921142578125) - (-0.0032958984375,0.921142578125) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.4447021484375,-0.1688232421875) - (-0.4447021484375,-0.1688232421875) - (0.9996337890625,0.000244140625) - (0.9996337890625,0.000244140625) - (0.4127197265625,-0.19140625) - (0.4127197265625,-0.19140625) - (-0.0379638671875,0.728759765625) - (-0.0379638671875,0.728759765625) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.617919921875,-0.0762939453125) - (-0.617919921875,-0.0762939453125) - (-0.6170654296875,0.0765380859375) - (-0.6170654296875,0.0765380859375) - (0.0621337890625,-0.654296875) - (0.0621337890625,-0.654296875) - (-0.127685546875,-0.511962890625) - (-0.127685546875,-0.511962890625) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.29296875,-0.293212890625) - (0.29296875,-0.293212890625) - (-0.01953125,-0.8046875) - (-0.01953125,-0.8046875) - (0.654296875,0.0618896484375) - (0.654296875,0.0618896484375) - (0.3505859375,-0.239990234375) - (0.3505859375,-0.239990234375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.805419921875,0.01953125) - (0.805419921875,0.01953125) - (0.1688232421875,-0.444580078125) - (0.1688232421875,-0.444580078125) -# name: pulse325 -# type: complex matrix -# rows: 320 -# columns: 1 - (-0.0003662109375,0.9998779296875) - (-0.0003662109375,0.9998779296875) - (0,-0.9996337890625) - (0,-0.9996337890625) - (-0.0010986328125,-0.961181640625) - (-0.0010986328125,-0.961181640625) - (0.0072021484375,0.882568359375) - (0.0072021484375,0.882568359375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.0765380859375,0.616943359375) - (0.0765380859375,0.616943359375) - (-0.1688232421875,-0.4447021484375) - (-0.1688232421875,-0.4447021484375) - (0.3212890625,0.26611328125) - (0.3212890625,0.26611328125) - (-0.54638671875,-0.1092529296875) - (-0.54638671875,-0.1092529296875) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.8046875,-0.019775390625) - (0.8046875,-0.019775390625) - (-0.444580078125,0.1688232421875) - (-0.444580078125,0.1688232421875) - (0.147705078125,-0.477294921875) - (0.147705078125,-0.477294921875) - (-0.0032958984375,0.921142578125) - (-0.0032958984375,0.921142578125) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.4447021484375,-0.1688232421875) - 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- f = fopen(name, "rb"); - s = zeros(1, vlen); - n = 0; - - while (!feof(f)) - t = fread(f, [2, vlen], "float"); - if (size(t) == [2, vlen]) - n = n+1; - c = t(1,:)+t(2,:)*j; - if (n > 10) - s = s+c; - endif - endif - endwhile - - avg = s/(n-1); - - fclose(f); - -endfunction diff --git a/gr-radar-mono/src/utils/read_avg_sec.m b/gr-radar-mono/src/utils/read_avg_sec.m deleted file mode 100644 index 7aa77675d..000000000 --- a/gr-radar-mono/src/utils/read_avg_sec.m +++ /dev/null @@ -1,25 +0,0 @@ -function avg = read_avg_sec(name, vlen) - - f = fopen(name, "rb"); - s = zeros(1, vlen); - n = 0; - m = 0; - - while (!feof(f)) - t = fread(f, [2, vlen], "float"); - if (size(t) == [2, vlen]) - n = n+1; - c = t(1,:)+t(2,:)*j; - s = s+c; - m = m+1; - if (m == 1000) - avg(n/1000,:) = s/1000; - s = zeros(1, vlen); - m = 0; - endif - endif - endwhile - - fclose(f); - -endfunction diff --git a/gr-radar-mono/src/utils/read_echos.m b/gr-radar-mono/src/utils/read_echos.m deleted file mode 100644 index 3fae47b4e..000000000 --- a/gr-radar-mono/src/utils/read_echos.m +++ /dev/null @@ -1,7 +0,0 @@ -# Read echos from file into array -function echos = read_echos(filename, len, drop) - e = read_complex_binary(filename); - n = length(e)/len-drop; - start = drop*len+1; - echos = reshape(e(start:end), len, n).'; -endfunction diff --git a/gr-sounder/.gitignore b/gr-sounder/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/Makefile.am b/gr-sounder/Makefile.am deleted file mode 100644 index 40b11dcea..000000000 --- a/gr-sounder/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = src doc diff --git a/gr-sounder/README b/gr-sounder/README deleted file mode 100644 index 3c5df21d4..000000000 --- a/gr-sounder/README +++ /dev/null @@ -1,91 +0,0 @@ -This is a work-in-progress implementation of a m-sequence based channel -sounder for GNU Radio and the USRP. - -In typical use, the user would run the sounder as a transmitter on one -USRP, and a receiver on another at a different location. The receiver -will determine the impulse response of the RF channel in between. - -The sounder uses a custom FPGA bitstream that is able to generate and -receive a sounder waveform across a full 32 MHz wide swath of RF spectrum; -the waveform generation and impulse response processing occur in logic in -the USRP FPGA and not in the host PC. This avoids the USB throughput -bottleneck entirely. Unfortunately, there is still roll-off in the AD9862 -digital up-converter interpolation filter that impacts the outer 20% of -bandwidth, but this can be compensated for by measuring and subtracting -out this response during calibration. - -The sounder is based on sending a maximal-length PN code modulated as BPSK -with the supplied center frequency, with a chip-rate of 32 MHz. The -receiver correlates the received signal across all phases of the PN code -and outputs an impulse response vector. As auto-correlation of an m-sequence -is near zero for any relative phase shift, the actual measured energy at a -particular phase shift is related to the impulse response for that time delay. -This is the same principle used in spread-spectrum RAKE receivers such as are -used with GPS and CDMA. - -The transmitter is designed to work only with the board in side A. The -receiver may be in side A or side B. The boards may be standalone LFTX/LFRXs -or RFX daughterboards. - -To use, the following script is installed into $prefix/bin: - -Usage: usrp_sounder.py [options] - -Options: - -h, --help show this help message and exit - -R RX_SUBDEV_SPEC, --rx-subdev-spec=RX_SUBDEV_SPEC - select USRP Rx side A or B - -f FREQ, --frequency=FREQ - set frequency to FREQ in Hz, default is 0.0 - -d DEGREE, --degree=DEGREE - set sounding sequence degree (2-12), default is 12, - -t, --transmit enable sounding transmitter - -r, --receive enable sounding receiver - -l, --loopback enable digital loopback, default is disabled - -v, --verbose enable verbose output, default is disabled - -D, --debug enable debugging output, default is disabled - -F FILENAME, --filename=FILENAME - log received impulse responses to file - -To use with an LFTX board, set the center frequency to 16M: - -$ usrp_sounder.py -f 16M -t - -The sounder receiver command line is: - -$ usrp_sounder.py -f 16M -r -F output.dat - -You can vary the m-sequence degree between 2 and 12, which will create -sequence lengths between 3 and 4095 (128 us). This will affect -how frequently the receiver can calculate impulse response vectors. - -The correlator uses an O(N^2) algorithm, by using an entire PN period -of the received signal to correlate at each lag value. Thus, using a -degree 12 PN code of length 4095, it takes 4095*4095/32e6 seconds to -calculate a single impulse response vector, about a half a second. One -can reduce this time by a factor of 4 for each decrement in PN code -degree, but this also reduces the inherent processing gain by 6 dB as -well. - -The impulse response vectors are written to a file in complex float -format, and consist of the actual impulse response with a noise floor -dependent on the PN code degree in use. - -There is a loopback test mode that causes the sounding waveform to be -routed back to the receiver inside the USRP: - -$ usrp_sounder.py -r -t -l -F output.dat - -The resulting impulse response will be a spike followed by a near zero -value for the rest of the period. - -Synchronization at the receiver is not yet implemented, so the actual -impulse response may be time shifted an arbitrary value within the the -impulse response vector. If one assumes the first to arrive signal is -the strongest, then one can circularly rotate the vector until the peak -is at time zero. - -Johnathan Corgan -Corgan Enterprises LLC -jcorgan@corganenterprises.com -5/28/07 diff --git a/gr-sounder/doc/.gitignore b/gr-sounder/doc/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/doc/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/doc/Makefile.am b/gr-sounder/doc/Makefile.am deleted file mode 100644 index 714ed52b9..000000000 --- a/gr-sounder/doc/Makefile.am +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - diff --git a/gr-sounder/src/.gitignore b/gr-sounder/src/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/src/Makefile.am b/gr-sounder/src/Makefile.am deleted file mode 100644 index d546da7f8..000000000 --- a/gr-sounder/src/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = fpga lib -if PYTHON -SUBDIRS += python -endif diff --git a/gr-sounder/src/fpga/.gitignore b/gr-sounder/src/fpga/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/src/fpga/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/src/fpga/Makefile.am b/gr-sounder/src/fpga/Makefile.am deleted file mode 100644 index 85256cb5e..000000000 --- a/gr-sounder/src/fpga/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = top lib tb diff --git a/gr-sounder/src/fpga/lib/.gitignore b/gr-sounder/src/fpga/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/src/fpga/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/src/fpga/lib/Makefile.am b/gr-sounder/src/fpga/lib/Makefile.am deleted file mode 100644 index a9586ebcc..000000000 --- a/gr-sounder/src/fpga/lib/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009,2010 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - dac_interface.v \ - dacpll.v \ - sounder.v \ - sounder_ctrl.v \ - sounder_rx.v \ - sounder_tx.v diff --git a/gr-sounder/src/fpga/lib/dac_interface.v b/gr-sounder/src/fpga/lib/dac_interface.v deleted file mode 100644 index 93c72cca6..000000000 --- a/gr-sounder/src/fpga/lib/dac_interface.v +++ /dev/null @@ -1,60 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../top/config.vh" - -module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o); - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - - input [13:0] tx_i_i; - input [13:0] tx_q_i; - - output [13:0] tx_data_o; - output tx_sync_o; - -`ifdef TX_RATE_MAX - wire clk128; - reg clk64_d; - reg [13:0] tx_data_o; - - // Create a 128 MHz clock - dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128)); - - // Register the clk64 clock in the clk128 domain - always @(posedge clk128) - clk64_d <= #1 clk_i; - - // Register the tx data in the clk128 domain - always @(posedge clk128) - tx_data_o <= #1 clk64_d ? tx_i_i : tx_q_i; - - assign tx_sync_o = clk64_d; - - -`else // !`ifdef TX_RATE_MAX - assign tx_data_o = strobe_i ? tx_q_i : tx_i_i; - assign tx_sync_o = strobe_i; -`endif // !`ifdef TX_RATE_MAX - -endmodule // dac_interface diff --git a/gr-sounder/src/fpga/lib/dacpll.v b/gr-sounder/src/fpga/lib/dacpll.v deleted file mode 100644 index 25f584f4f..000000000 --- a/gr-sounder/src/fpga/lib/dacpll.v +++ /dev/null @@ -1,291 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: dacpll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 7.0 Build 33 02/05/2007 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2007 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module dacpll ( - areset, - inclk0, - c0); - - input areset; - input inclk0; - output c0; - - wire [5:0] sub_wire0; - wire [0:0] sub_wire4 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire sub_wire2 = inclk0; - wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; - - altpll altpll_component ( - .inclk (sub_wire3), - .areset (areset), - .clk (sub_wire0), - .activeclock (), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b1), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbout (), - .locked (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.clk0_divide_by = 1, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 2, - altpll_component.clk0_phase_shift = "0000", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 15625, - altpll_component.intended_device_family = "Cyclone", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_USED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_UNUSED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" -// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/gr-sounder/src/fpga/lib/lfsr.v b/gr-sounder/src/fpga/lib/lfsr.v deleted file mode 100644 index bd0743e9c..000000000 --- a/gr-sounder/src/fpga/lib/lfsr.v +++ /dev/null @@ -1,46 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o); - parameter width = 16; - - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - input [width-1:0] mask_i; - - output pn_o; - - reg [width-1:0] shifter; - - wire parity = ^(shifter & mask_i); - - always @(posedge clk_i) - if (rst_i | ~ena_i) - shifter <= #5 1; - else - if (strobe_i) - shifter <= #5 {shifter[width-2:0],parity}; - - assign pn_o = shifter[0]; - -endmodule // lfsr diff --git a/gr-sounder/src/fpga/lib/lfsr_constants.v b/gr-sounder/src/fpga/lib/lfsr_constants.v deleted file mode 100644 index e23ed6601..000000000 --- a/gr-sounder/src/fpga/lib/lfsr_constants.v +++ /dev/null @@ -1,63 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module lfsr_constants(clk_i,rst_i,degree_i,mask_o,len_o); - input clk_i; - input rst_i; - input [4:0] degree_i; - output reg [15:0] mask_o; - output reg [16:0] len_o; - - integer len; - - always @(posedge clk_i) - if (rst_i) - begin - len_o <= #5 17'b0; - mask_o <= #5 16'b0; - end - else - begin - len_o <= #5 ((1 << degree_i) << 1)-3; - - case (degree_i) - 5'd00: mask_o <= #5 16'h0000; - 5'd01: mask_o <= #5 16'h0001; - 5'd02: mask_o <= #5 16'h0003; - 5'd03: mask_o <= #5 16'h0005; - 5'd04: mask_o <= #5 16'h0009; - 5'd05: mask_o <= #5 16'h0012; - 5'd06: mask_o <= #5 16'h0021; - 5'd07: mask_o <= #5 16'h0041; - 5'd08: mask_o <= #5 16'h008E; - 5'd09: mask_o <= #5 16'h0108; - 5'd10: mask_o <= #5 16'h0204; - 5'd11: mask_o <= #5 16'h0402; - 5'd12: mask_o <= #5 16'h0829; - 5'd13: mask_o <= #5 16'h100D; - 5'd14: mask_o <= #5 16'h2015; - 5'd15: mask_o <= #5 16'h4001; - 5'd16: mask_o <= #5 16'h8016; - default: mask_o <= #5 16'h0000; - endcase // case(degree_i) - end // else: !if(rst_i) - -endmodule // lfsr_constants diff --git a/gr-sounder/src/fpga/lib/sounder.v b/gr-sounder/src/fpga/lib/sounder.v deleted file mode 100644 index 675be8881..000000000 --- a/gr-sounder/src/fpga/lib/sounder.v +++ /dev/null @@ -1,90 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module sounder(clk_i, saddr_i, sdata_i, s_strobe_i, - tx_strobe_o, tx_dac_i_o, tx_dac_q_o, - rx_adc_i_i,rx_adc_q_i, - rx_strobe_o, rx_imp_i_o,rx_imp_q_o); - - // System interface - input clk_i; // Master clock @ 64 MHz - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - - // Transmit subsystem - output tx_strobe_o; // Generate an transmitter output sample - output [13:0] tx_dac_i_o; // I channel transmitter output to DAC - output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC - - // Receive subsystem - output rx_strobe_o; // Indicates output samples ready for Rx FIFO - input [15:0] rx_adc_i_i; // I channel input from ADC interface module - input [15:0] rx_adc_q_i; // Q channel input from ADC interface module - output [15:0] rx_imp_i_o; // I channel impulse response to Rx FIFO - output [15:0] rx_imp_q_o; // Q channel impulse response to Rx FIFO - - // Internal variables - wire reset; - wire transmit; - wire receive; - wire loopback; - - wire [4:0] degree; - wire [13:0] ampl; - wire [15:0] mask; - - wire ref_strobe; - wire sum_strobe; - sounder_ctrl master(.clk_i(clk_i),.rst_i(reset),.saddr_i(saddr_i), - .sdata_i(sdata_i),.s_strobe_i(s_strobe_i), - .reset_o(reset),.transmit_o(transmit),.receive_o(receive),.loopback_o(loopback), - .degree_o(degree),.ampl_o(ampl),.mask_o(mask),.tx_strobe_o(tx_strobe_o), - .rx_strobe_o(rx_strobe_o),.sum_strobe_o(sum_strobe),.ref_strobe_o(ref_strobe)); - - // Loopback implementation - wire [13:0] tx_i, tx_q; - wire [15:0] tx_i_ext, tx_q_ext; - wire [15:0] rx_i, rx_q; - - sign_extend #(14,16) tx_i_extender(tx_i, tx_i_ext); - sign_extend #(14,16) tx_q_extender(tx_q, tx_q_ext); - - assign tx_dac_i_o = loopback ? 14'b0 : tx_i; - assign tx_dac_q_o = loopback ? 14'b0 : tx_q; - assign rx_i = loopback ? tx_i_ext : rx_adc_i_i; - assign rx_q = loopback ? tx_q_ext : rx_adc_q_i; - - sounder_tx transmitter - ( .clk_i(clk_i),.rst_i(reset),.ena_i(transmit), - .strobe_i(tx_strobe_o),.mask_i(mask),.ampl_i(ampl), - .tx_i_o(tx_i),.tx_q_o(tx_q) ); - - sounder_rx receiver - ( .clk_i(clk_i),.rst_i(reset),.ena_i(receive), - .sum_strobe_i(sum_strobe),.ref_strobe_i(ref_strobe), - .mask_i(mask),.degree_i(degree), - .rx_in_i_i(rx_i),.rx_in_q_i(rx_q),.rx_i_o(rx_imp_i_o),.rx_q_o(rx_imp_q_o)); - -endmodule // sounder diff --git a/gr-sounder/src/fpga/lib/sounder_ctrl.v b/gr-sounder/src/fpga/lib/sounder_ctrl.v deleted file mode 100644 index 6e967a5ba..000000000 --- a/gr-sounder/src/fpga/lib/sounder_ctrl.v +++ /dev/null @@ -1,97 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module sounder_ctrl(clk_i,rst_i,saddr_i,sdata_i,s_strobe_i, - reset_o,transmit_o,receive_o,loopback_o, - degree_o,ampl_o,mask_o, - tx_strobe_o,rx_strobe_o,sum_strobe_o,ref_strobe_o); - - input clk_i; // Master clock @ 64 MHz - input rst_i; // Master synchronous reset - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - output reset_o; - output transmit_o; - output receive_o; - output loopback_o; - output [4:0] degree_o; - output [13:0] ampl_o; - output [15:0] mask_o; - output tx_strobe_o; - output rx_strobe_o; - output sum_strobe_o; - output ref_strobe_o; - - setting_reg #(`FR_USER_0) sr_mode - ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out({loopback_o,receive_o,transmit_o,reset_o}) ); - - setting_reg #(`FR_USER_1) sr_lfsr_degree - ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(degree_o) ); - - setting_reg #(`FR_USER_2) sr_lfsr_ampl - ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(ampl_o) ); - - wire [16:0] len; - lfsr_constants constants - (.clk_i(clk_i),.rst_i(rst_i),.degree_i(degree_o),.mask_o(mask_o), - .len_o(len) ); - - reg [15:0] phase; - assign tx_strobe_o = ~phase[0]; - assign ref_strobe_o = tx_strobe_o & !(phase>>1 == len>>1); - assign sum_strobe_o = (phase == len); - - reg rx_strobe_o; - always @(posedge clk_i) - if (rst_i) - begin - phase <= #5 16'hFFFF; - rx_strobe_o <= #5 0; - end - else - if (sum_strobe_o) - begin - phase <= #5 0; - rx_strobe_o <= #5 1'b1; - end - else - begin - phase <= #5 phase + 16'b1; - rx_strobe_o <= #5 0; - end - - - - - - - - - - -endmodule // sounder_ctrl diff --git a/gr-sounder/src/fpga/lib/sounder_rx.v b/gr-sounder/src/fpga/lib/sounder_rx.v deleted file mode 100644 index 18038a3a1..000000000 --- a/gr-sounder/src/fpga/lib/sounder_rx.v +++ /dev/null @@ -1,83 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module sounder_rx(clk_i,rst_i,ena_i,sum_strobe_i,ref_strobe_i, - mask_i,degree_i,rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o); - - input clk_i; // Master clock - input rst_i; // Subsystem reset - input ena_i; // Subsystem enable - input sum_strobe_i; // Strobe on last sample per period - input ref_strobe_i; // PN code reference retarded one sample per period - - input [15:0] mask_i; // PN code LFSR mask - input [4:0] degree_i; // PN code LFSR sequency degree - - input [15:0] rx_in_i_i; // I channel on receive - input [15:0] rx_in_q_i; // Q channel on receive - - output [15:0] rx_i_o; // I channel of impulse response - output [15:0] rx_q_o; // Q channel of impulse response - - reg [31:0] sum_i, sum_q; - reg [31:0] total_i, total_q; - wire [31:0] i_ext, q_ext; - - sign_extend #(16,32) i_extender(rx_in_i_i, i_ext); - sign_extend #(16,32) q_extender(rx_in_q_i, q_ext); - - wire pn_ref; - lfsr ref_code - ( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(ref_strobe_i),.mask_i(mask_i),.pn_o(pn_ref) ); - - wire [31:0] prod_i = pn_ref ? i_ext : -i_ext; - wire [31:0] prod_q = pn_ref ? q_ext : -q_ext; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - begin - sum_i <= #5 0; - sum_q <= #5 0; - total_i <= #5 0; - total_q <= #5 0; - end - else - if (sum_strobe_i) - begin - total_i <= #5 sum_i; - total_q <= #5 sum_q; - sum_i <= #5 prod_i; - sum_q <= #5 prod_q; - end - else - begin - sum_i <= #5 sum_i + prod_i; - sum_q <= #5 sum_q + prod_q; - end - - wire [5:0] offset = (5'd16-degree_i); - wire [31:0] scaled_i = total_i << offset; - wire [31:0] scaled_q = total_q << offset; - assign rx_i_o = scaled_i[31:16]; - assign rx_q_o = scaled_q[31:16]; - -endmodule // sounder_rx - diff --git a/gr-sounder/src/fpga/lib/sounder_tx.v b/gr-sounder/src/fpga/lib/sounder_tx.v deleted file mode 100644 index 148b1e500..000000000 --- a/gr-sounder/src/fpga/lib/sounder_tx.v +++ /dev/null @@ -1,44 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module sounder_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,mask_i,tx_i_o,tx_q_o); - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - input [13:0] ampl_i; - input [15:0] mask_i; - output [13:0] tx_i_o; - output [13:0] tx_q_o; - - wire pn; - wire [13:0] min_value = (~ampl_i)+14'b1; - - lfsr pn_code - ( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),.mask_i(mask_i),.pn_o(pn) ); - - assign tx_i_o = ena_i ? (pn ? ampl_i : min_value) : 14'b0; // Bipolar - assign tx_q_o = 14'b0; - -endmodule // sounder_tx diff --git a/gr-sounder/src/fpga/tb/.gitignore b/gr-sounder/src/fpga/tb/.gitignore deleted file mode 100644 index b05ab62aa..000000000 --- a/gr-sounder/src/fpga/tb/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/Makefile -/Makefile.in -/*.vcd -/sounder_tb -/*.out* diff --git a/gr-sounder/src/fpga/tb/Makefile.am b/gr-sounder/src/fpga/tb/Makefile.am deleted file mode 100644 index b21cb5f96..000000000 --- a/gr-sounder/src/fpga/tb/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009,2010 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - sounder_tb.v \ - sounder_tb.sav \ - sounder_tb.sh \ - sounder_tb_wave.sh - -MOSTLYCLEANFILES += *.vcd *.out* sounder_tb diff --git a/gr-sounder/src/fpga/tb/sounder_tb.sav b/gr-sounder/src/fpga/tb/sounder_tb.sav deleted file mode 100644 index 25bc512bc..000000000 --- a/gr-sounder/src/fpga/tb/sounder_tb.sav +++ /dev/null @@ -1,57 +0,0 @@ -*-29.807737 317080000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@200 -- -@28 -sounder_tb.s_strobe -@22 -sounder_tb.saddr[6:0] -@200 -- -@28 -sounder_tb.uut.reset -sounder_tb.uut.transmit -sounder_tb.uut.receive -sounder_tb.uut.loopback -@200 -- -@22 -sounder_tb.uut.degree[4:0] -sounder_tb.uut.mask[15:0] -sounder_tb.uut.ampl[13:0] -sounder_tb.uut.receiver.offset[5:0] -@200 -- -@8420 -sounder_tb.tx_dac_i[13:0] -@28 -sounder_tb.tx_strobe -@200 -- -@8420 -sounder_tb.fifo_i[15:0] -@28 -sounder_tb.fifo_strobe -@200 -- -@28 -sounder_tb.uut.ref_strobe -sounder_tb.uut.sum_strobe -@200 -- -@28 -sounder_tb.clk -sounder_tb.uut.transmitter.pn -sounder_tb.uut.receiver.pn_ref -@8420 -sounder_tb.uut.receiver.prod_i[31:0] -sounder_tb.uut.receiver.scaled_i[31:0] -@8421 -sounder_tb.uut.receiver.sum_i[31:0] -@8420 -sounder_tb.uut.receiver.total_i[31:0] -@200 -- -@22 -sounder_tb.uut.master.len[16:0] -@200 -- diff --git a/gr-sounder/src/fpga/tb/sounder_tb.sh b/gr-sounder/src/fpga/tb/sounder_tb.sh deleted file mode 100755 index 28efc8d31..000000000 --- a/gr-sounder/src/fpga/tb/sounder_tb.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -iverilog -y ../lib/ -y ../../../../usrp/fpga/sdr_lib \ - sounder_tb.v -o sounder_tb && \ -./sounder_tb > sounder_tb.out && \ - grep 'r=0' sounder_tb.out | grep 'c=1' > sounder_tb.out2 - diff --git a/gr-sounder/src/fpga/tb/sounder_tb.v b/gr-sounder/src/fpga/tb/sounder_tb.v deleted file mode 100644 index 0e0cb55c2..000000000 --- a/gr-sounder/src/fpga/tb/sounder_tb.v +++ /dev/null @@ -1,238 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`timescale 1ns/100ps - -`include "../lib/sounder.v" - -`define FR_MODE 7'd64 -`define bmFR_MODE_RESET 32'h0001 -`define bmFR_MODE_TX 32'h0002 -`define bmFR_MODE_RX 32'h0004 -`define bmFR_MODE_LP 32'h0008 - -`define FR_DEGREE 7'd65 -`define FR_AMPL 7'd66 - -module sounder_tb; - - // System bus - reg clk; - reg rst; - reg ena; - - // Configuration bus - reg [6:0] saddr; - reg [31:0] sdata; - reg s_strobe; - - // DAC bus - wire tx_strobe; - wire [13:0] tx_dac_i; - wire [13:0] tx_dac_q; - - // ADC bus - reg [15:0] rx_adc_i; - reg [15:0] rx_adc_q; - - // FIFO bus - wire fifo_strobe; - wire [15:0] fifo_i; - wire [15:0] fifo_q; - - // Configuration shadow registers - reg [31:0] mode; - reg [31:0] degree; - - sounder uut - (.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe), - .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q), - .rx_strobe_o(fifo_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q), - .rx_imp_i_o(fifo_i),.rx_imp_q_o(fifo_q)); - - // Start up initialization - initial - begin - clk = 0; - rst = 0; - ena = 0; - saddr = 0; - sdata = 0; - s_strobe = 0; - rx_adc_i = 0; - rx_adc_q = 0; - mode = 0; - degree = 0; - - @(posedge clk); - rst = 1; - @(posedge clk); - rst = 0; - @(posedge clk); - ena = 1; - end - - always - #5 clk <= ~clk; - - initial - begin - $monitor($time, " c=%b r=%b phs=%d txs=%b rfs=%b rxs=%b sms=%b pn=%b pnr=%b prd=%x sum=%x tot=%x", - clk, rst, uut.master.phase, uut.tx_strobe_o, uut.ref_strobe, uut.rx_strobe_o, - uut.sum_strobe, uut.transmitter.pn, uut.receiver.pn_ref, uut.receiver.prod_i, - uut.receiver.sum_i, uut.receiver.total_i); - - $dumpfile("sounder_tb.vcd"); - $dumpvars(0, sounder_tb); - end - - // Test tasks - task write_cfg_register; - input [6:0] regno; - input [31:0] value; - - begin - @(posedge clk); - saddr <= #5 regno; - sdata <= #5 value; - s_strobe <= #5 1'b1; - @(posedge clk); - s_strobe <= #5 0; - end - endtask // write_cfg_register - - // Application reset line - task set_reset; - input reset; - - begin - mode = reset ? (mode | `bmFR_MODE_RESET) : (mode & ~`bmFR_MODE_RESET); - write_cfg_register(`FR_MODE, mode); - end - endtask // reset - - // Set the PN code degree - task set_degree; - input [5:0] degree; - begin - write_cfg_register(`FR_DEGREE, degree); - end - endtask // set_degree - - // Set the PN amplitude - task set_amplitude; - input [13:0] ampl; - begin - write_cfg_register(`FR_AMPL, ampl); - end - endtask // set_ampl - - // Turn on or off the transmitter - task enable_tx; - input tx; - - begin - mode = tx ? (mode | `bmFR_MODE_TX) : (mode & ~`bmFR_MODE_TX); - write_cfg_register(`FR_MODE, mode); - end - endtask // enable_tx - - // Turn on or off the receiver - task enable_rx; - input rx; - - begin - mode = rx ? (mode | `bmFR_MODE_RX) : (mode & ~`bmFR_MODE_RX); - write_cfg_register(`FR_MODE, mode); - end - endtask // enable_rx - - - // Turn on or off digital loopback - task enable_lp; - input lp; - - begin - mode = lp ? (mode | `bmFR_MODE_LP) : (mode & ~`bmFR_MODE_LP); - write_cfg_register(`FR_MODE, mode); - end - endtask // enable_lp - - // Test transmitter functionality - task test_tx; - input [5:0] degree; - input [31:0] test_len; - - begin - #20 set_reset(1); - #20 set_degree(degree); - #20 set_amplitude(14'h1000); - #20 enable_tx(1); - #20 enable_rx(0); - #20 enable_lp(0); - #20 set_reset(0); - #(test_len); - end - endtask // test_tx - - // Test loopback functionality - task test_lp; - input [5:0] degree; - input [31:0] test_len; - - begin - #20 set_reset(1); - #20 set_degree(degree); - #20 enable_tx(1); - #20 enable_rx(1); - #20 enable_lp(1); - #20 set_reset(0); - #(test_len); - end - endtask // test_lp - - // Test receiver only functionality - task test_rx; - input [5:0] degree; - input [31:0] test_len; - - begin - #20 set_reset(1); - #20 set_degree(degree); - #20 enable_tx(0); - #20 enable_rx(1); - #20 enable_lp(0); - #20 set_reset(0); - #(test_len); - end - endtask // test_rx - - // Execute tests - initial - begin - #20 test_tx(8,255*20); - #20 test_lp(8,255*255*20*5); - //#20 test_rx(8,255*255*20*5); - #500 $finish; - end - -endmodule - diff --git a/gr-sounder/src/fpga/tb/sounder_tb_wave.sh b/gr-sounder/src/fpga/tb/sounder_tb_wave.sh deleted file mode 100755 index 4551d5c59..000000000 --- a/gr-sounder/src/fpga/tb/sounder_tb_wave.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -gtkwave sounder_tb.vcd sounder_tb.sav diff --git a/gr-sounder/src/fpga/top/.gitignore b/gr-sounder/src/fpga/top/.gitignore deleted file mode 100644 index 2c9458cf2..000000000 --- a/gr-sounder/src/fpga/top/.gitignore +++ /dev/null @@ -1,11 +0,0 @@ -/Makefile -/Makefile.in -/db -/*.rpt -/*.summary -/*.rbf -/*.qws -/*.smsg -/*.done -/*.pin -/*.sof diff --git a/gr-sounder/src/fpga/top/Makefile.am b/gr-sounder/src/fpga/top/Makefile.am deleted file mode 100644 index f559991de..000000000 --- a/gr-sounder/src/fpga/top/Makefile.am +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -RBFS = usrp_sounder.rbf - -rbf2datadir = $(prefix)/share/usrp/rev2 -dist_rbf2data_DATA = $(RBFS) - -rbf4datadir = $(prefix)/share/usrp/rev4 -dist_rbf4data_DATA = $(RBFS) - -EXTRA_DIST += \ - config.vh \ - usrp_sounder.v \ - usrp_sounder.csf \ - usrp_sounder.esf \ - usrp_sounder.psf \ - usrp_sounder.qpf - -MOSTLYCLEANFILES += \ - db/* \ - *.rpt \ - *.summary \ - *.qws \ - *.smsg \ - *.done \ - *.pin \ - *.sof diff --git a/gr-sounder/src/fpga/top/config.vh b/gr-sounder/src/fpga/top/config.vh deleted file mode 100644 index 06445e9af..000000000 --- a/gr-sounder/src/fpga/top/config.vh +++ /dev/null @@ -1,22 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz -//`define TX_RATE_MAX diff --git a/gr-sounder/src/fpga/top/usrp_sounder.csf b/gr-sounder/src/fpga/top/usrp_sounder.csf deleted file mode 100644 index 544f278e3..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_sounder; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_sounder) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/gr-sounder/src/fpga/top/usrp_sounder.esf b/gr-sounder/src/fpga/top/usrp_sounder.esf deleted file mode 100644 index c7d828b2b..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_sounder; -} diff --git a/gr-sounder/src/fpga/top/usrp_sounder.psf b/gr-sounder/src/fpga/top/usrp_sounder.psf deleted file mode 100644 index 7bd32ff59..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_sounder) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_sounder) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>"; - EDA_SIMULATION_TOOL = "<NONE>"; - EDA_TIMING_ANALYSIS_TOOL = "<NONE>"; - EDA_BOARD_DESIGN_TOOL = "<NONE>"; - EDA_FORMAL_VERIFICATION_TOOL = "<NONE>"; - EDA_RESYNTHESIS_TOOL = "<NONE>"; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qpf b/gr-sounder/src/fpga/top/usrp_sounder.qpf deleted file mode 100644 index aa75e962b..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "7.0" -DATE = "09:00:00 April 17, 2007" - - -# Active Revisions - -PROJECT_REVISION = "usrp_sounder" diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qsf b/gr-sounder/src/fpga/top/usrp_sounder.qsf deleted file mode 100644 index 4d60f5f13..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.qsf +++ /dev/null @@ -1,396 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# usrp_sounder_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 7.0
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Timing Assignments
-# ==================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_sounder
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# -----------------
-# start CLOCK(SCLK)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# -----------------------
-# start CLOCK(master_clk)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# -------------------
-# start CLOCK(usbclk)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# ----------------------
-# start ENTITY(usrp_sounder)
-
- # Timing Assignments
- # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-# end ENTITY(usrp_sounder)
-# --------------------
-
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC
-set_global_assignment -name VERILOG_FILE ../lib/lfsr_constants.v
-set_global_assignment -name VERILOG_FILE ../lib/lfsr.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/sounder_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/sounder_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/sounder_ctrl.v
-set_global_assignment -name VERILOG_FILE ../lib/sounder.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sounder.v
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file diff --git a/gr-sounder/src/fpga/top/usrp_sounder.rbf b/gr-sounder/src/fpga/top/usrp_sounder.rbf Binary files differdeleted file mode 100755 index e2c9db6c4..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.rbf +++ /dev/null diff --git a/gr-sounder/src/fpga/top/usrp_sounder.v b/gr-sounder/src/fpga/top/usrp_sounder.v deleted file mode 100644 index a88b2388e..000000000 --- a/gr-sounder/src/fpga/top/usrp_sounder.v +++ /dev/null @@ -1,198 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins -// for debugging info. NB, This can kill the m'board and/or d'board if you -// have anything except basic d'boards installed. - -// Uncomment the following to include optional circuitry - -module usrp_sounder -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64; - - // wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_pkt_rdy; - assign usbrdy[0] = 1'b0; // have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = 1'b0; // tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] rx_numchan; - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - // TX - wire tx_sample_strobe; - wire tx_empty; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side - - wire [13:0] tx_i, tx_q; - wire [13:0] tx_dac; - - dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx), - .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q), - .tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A)); - - assign tx_a = tx_dac; - - // Wedge DAC #2 at zero - assign TXSYNC_B = 1'b0; - assign tx_b = 14'b0; - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side - wire rx_sample_strobe, rx_strobe; - wire [15:0] rx_adc0_i, rx_adc0_q; - wire [15:0] rx_buf_i, rx_buf_q; - - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(), - .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(), - .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q), - .ddc1_in_i(),.ddc1_in_q(), - .ddc2_in_i(),.ddc2_in_q(), - .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(rx_buf_i),.ch_1(rx_buf_q), - .ch_2(),.ch_3(), - .ch_4(),.ch_5(), - .ch_6(),.ch_7(), - .rxclk(clk64),.rxstrobe(rx_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus() ); - - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Top level application - - sounder sounder - ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe), - .tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q), - .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q), - .rx_strobe_o(rx_strobe),.rx_imp_i_o(rx_buf_i),.rx_imp_q_o(rx_buf_q) - ); - - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = 0; // `TX_CAP_HB; - assign capabilities[6:4] = 2; // `TX_CAP_NCHAN; - assign capabilities[3] = 0; // `RX_CAP_HB; - assign capabilities[2:0] = 2; // `RX_CAP_NCHAN; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(),.readback_5(),.readback_6(),.readback_7() - ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(),.decim_rate(), - .tx_sample_strobe(),.strobe_interp(), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(), - .tx_empty(tx_empty), - .debug_0(),.debug_1(), - .debug_2(),.debug_3(), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - -endmodule // usrp_sounder diff --git a/gr-sounder/src/lib/.gitignore b/gr-sounder/src/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-sounder/src/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-sounder/src/lib/Makefile.am b/gr-sounder/src/lib/Makefile.am deleted file mode 100644 index 4f35e3aef..000000000 --- a/gr-sounder/src/lib/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common diff --git a/gr-sounder/src/python/.gitignore b/gr-sounder/src/python/.gitignore deleted file mode 100644 index 8ac573ba1..000000000 --- a/gr-sounder/src/python/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/Makefile -/Makefile.in -/run_tests -/*.pyc -/loopback.dat diff --git a/gr-sounder/src/python/Makefile.am b/gr-sounder/src/python/Makefile.am deleted file mode 100644 index 1d9b25254..000000000 --- a/gr-sounder/src/python/Makefile.am +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -# Install this stuff so that it ends up as the gnuradio.sounder module -# This usually ends up at: -# ${prefix}/lib/python${python_version}/site-packages/gnuradio - -sounder_pythondir = $(grpythondir) - -EXTRA_DIST += \ - sounder_loopback.sh \ - qa_nothing.py \ - run_tests.in - -dist_bin_SCRIPTS = \ - usrp_sounder.py - -sounder_python_PYTHON = \ - sounder.py diff --git a/gr-sounder/src/python/qa_nothing.py b/gr-sounder/src/python/qa_nothing.py deleted file mode 100644 index e69de29bb..000000000 --- a/gr-sounder/src/python/qa_nothing.py +++ /dev/null diff --git a/gr-sounder/src/python/run_tests.in b/gr-sounder/src/python/run_tests.in deleted file mode 100644 index b8f7830c2..000000000 --- a/gr-sounder/src/python/run_tests.in +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -# 1st parameter is absolute path to component source directory -# 2nd parameter is absolute path to component build directory -# 3rd parameter is path to Python QA directory - -@top_builddir@/run_tests.sh \ - @abs_top_srcdir@/gr-sounder \ - @abs_top_builddir@/gr-sounder \ - @srcdir@ diff --git a/gr-sounder/src/python/sounder.py b/gr-sounder/src/python/sounder.py deleted file mode 100644 index 85c03b0e1..000000000 --- a/gr-sounder/src/python/sounder.py +++ /dev/null @@ -1,271 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, usrp -from gnuradio import eng_notation - -n2s = eng_notation.num_to_str - -FR_MODE = usrp.FR_USER_0 -bmFR_MODE_RESET = 1 << 0 # bit 0: active high reset -bmFR_MODE_TX = 1 << 1 # bit 1: enable transmitter -bmFR_MODE_RX = 1 << 2 # bit 2: enable receiver -bmFR_MODE_LP = 1 << 3 # bit 3: enable digital loopback - -FR_DEGREE = usrp.FR_USER_1 -FR_AMPL = usrp.FR_USER_2 - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem - return (0, 0) - if u.db[1][0].dbid() >= 0: - return (1, 0) - return (0, 0) - -class sounder_tx: - def __init__(self, loopback=False,ampl=4096,verbose=False,debug=False): - self._loopback=loopback - self._amplitude = ampl - self._verbose = verbose - self._debug = debug - self._u = usrp.sink_s(fpga_filename='usrp_sounder.rbf') - if not self._loopback: - self._subdev_spec = usrp.pick_tx_subdevice(self._u) - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - if self._verbose: - print "Using", self._subdev.name(), "for sounder transmitter." - self.set_amplitude(ampl) - if not self._loopback: - self._subdev.set_lo_offset(0.0) - self._u.start() - if not self._loopback: - self._subdev.set_enable(True) - - def tune(self, frequency): - if self._verbose: - print "Setting transmitter frequency to", n2s(frequency) - result = self._u.tune(0, self._subdev, frequency) - if result == False: - raise RuntimeError("Failed to set transmitter frequency.") - - def set_amplitude(self, ampl): - self._amplitude = ampl - if self._debug: - print "Writing amplitude register with:", hex(self._mode) - self._u._write_fpga_reg(FR_AMPL, self._amplitude) - -class sounder_rx: - def __init__(self,subdev_spec=None,gain=None,length=1,alpha=1.0,msgq=None,loopback=False,verbose=False,debug=False): - self._subdev_spec = subdev_spec - self._gain = gain - self._length = length - self._alpha = alpha - self._msgq = msgq - self._loopback = loopback - self._verbose = verbose - self._debug = debug - - self._tb = gr.top_block() - self._u = usrp.source_c(fpga_filename='usrp_sounder.rbf') - if not self._loopback: - if self._subdev_spec == None: - self._subdev_spec = pick_subdevice(self._u) - self._u.set_mux(usrp.determine_rx_mux_value(self._u, self._subdev_spec)) - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - if self._verbose: - print "Using", self._subdev.name(), "for sounder receiver." - - self.set_gain(self._gain) - self._vblen = gr.sizeof_gr_complex*self._length - if self._debug: - print "Generating impulse vectors of length", self._length, "byte length", self._vblen - - self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length) - if self._verbose: - print "Using smoothing alpha of", self._alpha - self._lpf = gr.single_pole_iir_filter_cc(self._alpha, self._length) - self._sink = gr.message_sink(self._vblen, self._msgq, True) - self._tb.connect(self._u, self._s2v, self._lpf, self._sink) - - def tune(self, frequency): - if self._verbose: - print "Setting receiver frequency to", n2s(frequency) - result = self._u.tune(0, self._subdev, frequency) - if result == False: - raise RuntimeError("Failed to set receiver frequency.") - - def set_gain(self, gain): - self._gain = gain - if self._loopback: - return - - if self._gain is None: - # if no gain was specified, use the mid-point in dB - g = self._subdev.gain_range() - self._gain = float(g[0]+g[1])/2 - if self._verbose: - print "Setting receiver gain to", gain - self._subdev.set_gain(self._gain) - - def start(self): - if self._debug: - print "Starting receiver flow graph." - self._tb.start() - - def wait(self): - if self._debug: - print "Waiting for threads..." - self._tb.wait() - - def stop(self): - if self._debug: - print "Stopping receiver flow graph." - self._tb.stop() - self.wait() - if self._debug: - print "Receiver flow graph stopped." - - -class sounder: - def __init__(self,transmit=False,receive=False,loopback=False,rx_subdev_spec=None,ampl=0x1FFF, - frequency=0.0,rx_gain=None,degree=12,length=1,alpha=1.0,msgq=None,verbose=False,debug=False): - self._transmit = transmit - self._receive = receive - self._loopback = loopback - self._rx_subdev_spec = rx_subdev_spec - self._frequency = frequency - self._amplitude = ampl - self._rx_gain = rx_gain - self._degree = degree - self._length = length - self._alpha = alpha - self._msgq = msgq - self._verbose = verbose - self._debug = debug - self._mode = 0 - self._u = None - self._trans = None - self._rcvr = None - self._transmitting = False - self._receiving = False - - if self._transmit: - self._trans = sounder_tx(loopback=self._loopback,ampl=self._amplitude, - verbose=self._verbose) - self._u = self._trans._u - - if self._receive: - self._rcvr = sounder_rx(subdev_spec=self._rx_subdev_spec,length=self._length, - gain=self._rx_gain,alpha=self._alpha,msgq=self._msgq, - loopback=self._loopback,verbose=self._verbose, - debug=self._debug) - self._u = self._rcvr._u # either receiver or transmitter object will do - - self.set_reset(True) - if self._loopback == False: - self.tune(self._frequency) - self.set_degree(self._degree) - self.set_loopback(self._loopback) - self.set_reset(False) - - def tune(self, frequency): - self._frequency = frequency - if self._rcvr: - self._rcvr.tune(frequency) - if self._trans: - self._trans.tune(frequency) - - def set_degree(self, degree): - if self._verbose: - print "Setting PN code degree to", degree - self._u._write_fpga_reg(FR_DEGREE, degree); - - def _write_mode(self): - if self._debug: - print "Writing mode register with:", hex(self._mode) - self._u._write_fpga_reg(FR_MODE, self._mode) - - def enable_tx(self, value): - if value: - if self._verbose: - print "Enabling transmitter." - self._mode |= bmFR_MODE_TX - self._transmitting = True - else: - if self._verbose: - print "Disabling transmitter." - self._mode &= ~bmFR_MODE_TX - self._write_mode() - - def enable_rx(self, value): - if value: - self._mode |= bmFR_MODE_RX - self._write_mode() - self._rcvr.start() - self._receiving = True - else: - self._rcvr.stop() - self._mode &= ~bmFR_MODE_RX - self._write_mode() - self._receiving = False - - def set_loopback(self, value): - if value: - if self._verbose: - print "Enabling digital loopback." - self._mode |= bmFR_MODE_LP - else: - if self._verbose: - print "Disabling digital loopback." - self._mode &= ~bmFR_MODE_LP - self._write_mode() - - def set_reset(self, value): - if value: - if self._debug: - print "Asserting reset." - self._mode |= bmFR_MODE_RESET - else: - if self._debug: - print "De-asserting reset." - self._mode &= ~bmFR_MODE_RESET - self._write_mode() - - def start(self): - if self._transmit: - self.enable_tx(True) - if self._receive: - self.enable_rx(True) - - def __del__(self): - if self._transmitting: - self.enable_tx(False) - - if self._receiving: - self.enable_rx(False) - diff --git a/gr-sounder/src/python/sounder_loopback.sh b/gr-sounder/src/python/sounder_loopback.sh deleted file mode 100755 index a97a8fdcf..000000000 --- a/gr-sounder/src/python/sounder_loopback.sh +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -# Note this runs the installed script, not the one in the tree -usrp_sounder.py -r -l -t -d12 -v -F loopback.dat -D diff --git a/gr-sounder/src/python/usrp_sounder.py b/gr-sounder/src/python/usrp_sounder.py deleted file mode 100755 index c183ee85a..000000000 --- a/gr-sounder/src/python/usrp_sounder.py +++ /dev/null @@ -1,112 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr -from gnuradio.sounder import sounder -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import numpy -import sys - -n2s = eng_notation.num_to_str - -def main(): - parser = OptionParser(option_class=eng_option) - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=(0, 0), - help="select USRP Rx side A or B") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-f", "--frequency", type="eng_float", default=0.0, - help="set frequency to FREQ in Hz, default is %default", metavar="FREQ") - parser.add_option("-d", "--degree", type="int", default=12, - help="set sounding sequence degree (2-12), default is %default,") - parser.add_option("-a", "--amplitude", type="int", default=4096, - help="set waveform amplitude, default is %default,") - parser.add_option("-t", "--transmit", action="store_true", default=False, - help="enable sounding transmitter") - parser.add_option("-r", "--receive", action="store_true", default=False, - help="enable sounding receiver") - parser.add_option("-l", "--loopback", action="store_true", default=False, - help="enable digital loopback, default is disabled") - parser.add_option("-v", "--verbose", action="store_true", default=False, - help="enable verbose output, default is disabled") - parser.add_option("-D", "--debug", action="store_true", default=False, - help="enable debugging output, default is disabled") - parser.add_option("-F", "--filename", default=None, - help="log received impulse responses to file") - parser.add_option("", "--alpha", type="eng_float", default=1.0, - help="smoothing factor (0.0-1.0), default is %default (none)") - - (options, args) = parser.parse_args() - - if len(args) != 0 or not (options.transmit | options.receive): - parser.print_help() - sys.exit(1) - - if options.receive and (options.filename == None): - print "Must supply filename when receiving." - sys.exit(1) - - if options.degree > 12 or options.degree < 2: - print "PN code degree must be between 2 and 12" - sys.exit(1) - - length = int(2**options.degree-1) - if options.verbose: - print "Using PN code degree of", options.degree, "length", length - if options.loopback == False: - print "Sounding frequency range is", n2s(options.frequency-16e6), "to", n2s(options.frequency+16e6) - if options.filename != None: - print "Logging impulse records to file: ", options.filename - - msgq = gr.msg_queue() - s = sounder(transmit=options.transmit,receive=options.receive, - loopback=options.loopback,rx_subdev_spec=options.rx_subdev_spec, - frequency=options.frequency,rx_gain=options.gain, - degree=options.degree,length=length,alpha=options.alpha, - msgq=msgq,verbose=options.verbose,ampl=options.amplitude, - debug=options.debug) - s.start() - - if options.receive: - f = open(options.filename, "wb") - print "Enter CTRL-C to stop." - try: - while (1): - msg = msgq.delete_head() - if msg.type() == 1: - break - rec = msg.to_string()[:length*gr.sizeof_gr_complex] - if options.debug: - print "Received impulse vector of length", len(rec) - - f.write(rec) - - except KeyboardInterrupt: - pass - else: - if options.transmit: - raw_input("Press return to exit.") - -if __name__ == "__main__": - main() diff --git a/version.sh b/version.sh index 759d52806..642c1baf8 100644 --- a/version.sh +++ b/version.sh @@ -1,4 +1,4 @@ MAJOR_VERSION=3 -API_COMPAT=4 -MINOR_VERSION=1 -MAINT_VERSION=git +API_COMPAT=5 +MINOR_VERSION=0 +MAINT_VERSION=0
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