logic to interface locallink fifos to our mac

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10739 221aa14e-8319-0410-a670-987f0aec2ac5

5 files changed, 264 insertions, 77 deletions

diff --git a/usrp2/fpga/simple_gemac/eth_tasks.v b/usrp2/fpga/simple_gemac/eth_tasks.v
new file mode 100644
index 000000000..f13d75f3b
--- /dev/null
+++ b/usrp2/fpga/simple_gemac/eth_tasks.v
@@ -0,0 +1,141 @@
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge clk);
+      pause_req <= 1;
+      @(posedge clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket2MAC;
+   input tx_clk;
+   input [7:0] data_start;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count <= 1;
+      tx_data  <= data_start;
+      tx_error <= 0;
+      tx_valid <= 1;
+      while(~tx_ack)
+	@(posedge tx_clk);
+      $display("Packet Accepted, %d", $time);
+      while(count < data_len)
+	begin
+	   tx_data <= tx_data + 1;
+	   count   <= count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge tx_clk);
+   end
+endtask // SendPacket2MAC
+
+task SendPacket_to_ll8;
+   input [7:0] data_start;
+   input [15:0] data_len;
+//   output [7:0] tx_data;
+//   output tx_sof;
+//   output tx_eof;
+//   output tx_src_rdy;
+//   input tx_dst_rdy;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_ll_data2 <= data_start;
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2  <= 1;
+      tx_ll_eof2  <= 0;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   @(posedge clk);
+	   tx_ll_data2 = tx_ll_data2 + 1;
+	   count   = count + 1;
+	   tx_ll_sof2 <= 0;
+	end
+      tx_ll_eof2 	   <= 1;
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacket_to_ll8
+
+
+task SendPacketFromFile;
+   input clk;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet From File Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+      count 	  = 0;
+      tx_data  = pkt_rom[count];
+      tx_error = 0;
+      tx_valid = 1;
+      while(~tx_ack)
+	@(posedge clk);
+      $display("Packet Accepted, %d",$time);
+      count = 1;
+      while(count < data_len)
+	begin
+	   tx_data = pkt_rom[count];
+	   count   = count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge clk);
+   end
+endtask // SendPacketFromFile
+
+task SendPacketFromFile_ll8;
+   input [31:0] data_len;
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_data2 <= pkt_rom[0];
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2     <= 1;
+      tx_ll_eof2     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacketFromFile_ll8
diff --git a/usrp2/fpga/simple_gemac/ll8_shortfifo.v b/usrp2/fpga/simple_gemac/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/usrp2/fpga/simple_gemac/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+  (input clk, input reset, input clear,
+   input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+   output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+   fifo_short #(.WIDTH(11)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
diff --git a/usrp2/fpga/simple_gemac/ll8_to_txmac.v b/usrp2/fpga/simple_gemac/ll8_to_txmac.v
new file mode 100644
index 000000000..3530a0c59
--- /dev/null
+++ b/usrp2/fpga/simple_gemac/ll8_to_txmac.v
@@ -0,0 +1,43 @@
+
+module ll8_to_txmac
+  (input clk, input reset, input clear,
+   input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output ll_dst_rdy,
+   output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack );
+
+   reg [2:0] xfer_state;
+
+   localparam XFER_IDLE      = 0;
+   localparam XFER_ACTIVE    = 1;
+   localparam XFER_WAIT1     = 2;
+   localparam XFER_UNDERRUN  = 3;
+   localparam XFER_DROP      = 4;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	    <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(tx_ack)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(~ll_src_rdy)
+	     xfer_state <= XFER_UNDERRUN;
+	   else if(ll_eof)
+	     xfer_state <= XFER_WAIT1;
+	 XFER_WAIT1 :
+	   xfer_state <= XFER_IDLE;
+	 XFER_UNDERRUN :
+	   xfer_state <= XFER_DROP;
+	 XFER_DROP :
+	   if(ll_eof)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   assign ll_dst_rdy 	 = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP);
+   assign tx_valid 	 = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE);
+   assign tx_data 	 = ll_data;
+   assign tx_error 	 = (xfer_state == XFER_UNDERRUN);
+   
+endmodule // ll8_to_txmac
+
diff --git a/usrp2/fpga/simple_gemac/rxmac_to_ll8.v b/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
new file mode 100644
index 000000000..9a795b257
--- /dev/null
+++ b/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
@@ -0,0 +1,42 @@
+
+module rxmac_to_ll8
+  (input clk, input reset, input clear,
+   input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
+   output [7:0] ll_data, output ll_sof, output ll_eof, output ll_src_rdy, input ll_dst_rdy );
+
+   assign ll_data 	= rx_data;
+   assign ll_src_rdy 	= rx_valid;
+   assign ll_sof 	= ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
+   assign ll_eof 	= (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
+   
+   reg [1:0] xfer_state;
+   localparam XFER_IDLE     = 0;
+   localparam XFER_ACTIVE   = 1;
+   localparam XFER_ERROR    = 2;
+   localparam XFER_OVERRUN  = 3;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	   <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(rx_valid)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(rx_error)
+	     xfer_state <= XFER_ERROR;
+	   else if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+	   else if(~ll_dst_rdy)
+	     xfer_state <= XFER_OVERRUN;
+	 XFER_ERROR :
+	   if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+	 XFER_OVERRUN :
+	   if(ll_dst_rdy & ~rx_valid)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   
+endmodule // rxmac_to_ll8
diff --git a/usrp2/fpga/simple_gemac/simple_gemac_tb.v b/usrp2/fpga/simple_gemac/simple_gemac_tb.v
index ff90c8d13..2465cce69 100644
--- a/usrp2/fpga/simple_gemac/simple_gemac_tb.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_tb.v
@@ -1,7 +1,7 @@
 
 
 module simple_gemac_tb;
-
+`include "eth_tasks.v"
      
    reg clk = 0;
    reg reset = 1;
@@ -61,16 +61,20 @@ module simple_gemac_tb;
    assign rx_ll_dst_rdy2 	= 1;
 
    wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire [7:0] tx_ll_data, tx_ll_data2;
-   wire tx_ll_error, tx_ll_error2;
+   reg tx_ll_sof2=0, tx_ll_eof2=0;
+   reg tx_ll_src_rdy2 = 0;
+   wire tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data;
+   reg [7:0] tx_ll_data2 = 0;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
 
    ll8_shortfifo tx_sfifo
      (.clk(clk), .reset(reset), .clear(clear),
-      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_sof2),
-      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_i(tx_ll_dst_rdy2),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
-      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_o(tx_ll_dst_rdy));
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
    
    ll8_to_txmac ll8_to_txmac
      (.clk(clk), .reset(reset), .clear(clear),
@@ -78,66 +82,6 @@ module simple_gemac_tb;
       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
       .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
 
-   task SendFlowCtrl;
-      input [15:0] fc_len;
-      begin
-	 $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
-	 pause_time = fc_len;
-	 @(posedge clk);
-	 pause_req <= 1;
-	 @(posedge clk);
-	 pause_req <= 0;
-      end
-   endtask // SendFlowCtrl
-   
-   reg [31:0] count;
-   task SendPacket;
-      input [7:0] data_start;
-      input [31:0] data_len;
-      begin
-	 $display("Sending Packet Len=%d, %d", data_len, $time);
-	 count <= 1;
-	 tx_data  <= data_start;
-	 tx_error <= 0;
-	 tx_valid <= 1;
-	 while(~tx_ack)
-	   @(posedge tx_clk);
-	 $display("Packet Accepted, %d", $time);
-	 while(count < data_len)
-	   begin
-	      tx_data <= tx_data + 1;
-	      count   <= count + 1;
-	      @(posedge clk);
-	   end
-	 tx_valid <= 0;
-	 @(posedge tx_clk);
-      end
-   endtask // SendPacket
-   	
-   task SendPacketFromFile;
-      input [31:0] data_len;
-      begin
-	 $display("Sending Packet From File Len=%d, %d",data_len,$time);
-	 $readmemh( "test_packet.mem",pkt_rom );     
-	 count 	  = 0;
-	 tx_data  = pkt_rom[count];
-	 tx_error = 0;
-	 tx_valid = 1;
-	 while(~tx_ack)
-	   @(posedge tx_clk);
-	 $display("Packet Accepted, %d",$time);
-	 count = 1;
-	 while(count < data_len)
-	   begin
-	      tx_data = pkt_rom[count];
-	      count   = count + 1;
-	      @(posedge clk);
-	   end
-	 tx_valid <= 0;
-	 @(posedge tx_clk);
-      end
-   endtask // SendPacket
-   	
    initial $dumpfile("simple_gemac_tb.vcd");
    initial $dumpvars(0,simple_gemac_tb);
 
@@ -155,36 +99,40 @@ module simple_gemac_tb;
 	repeat (10)
 	  @(posedge clk);
 	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge clk);
 	#30000;
 	@(posedge clk);
 	SendFlowCtrl(16'h0009);  // Increas flow control before it expires
 	#10000;
 	@(posedge clk);
 	SendFlowCtrl(16'h0000);  // Cancel flow control befor it expires
-	@(posedge clk);
-	SendPacket(8'hAA,10);    // This packet gets dropped by the filters
+	@(posedge clk); 
+
+	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile(60);  // The rest are valid packets
+
+ 	SendPacketFromFile_ll8(60);  // The rest are valid packets
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile(61);
+
+ 	SendPacketFromFile_ll8(61);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile(62);
+	SendPacketFromFile_ll8(62);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile(63);
+	SendPacketFromFile_ll8(63);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile(64);
+	SendPacketFromFile_ll8(64);
 	repeat (10)
 	  @(posedge clk);
-	SendPacketFromFile(59);
+	SendPacketFromFile_ll8(59);
 	repeat (1)
 	  @(posedge clk);
-	SendPacketFromFile(58);
-	#10000 $finish;
+	SendPacketFromFile_ll8(58);
+	#100000 $finish;
      end
 
    /*