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authorMatt Ettus2009-09-03 21:39:48 -0700
committerMatt Ettus2009-09-03 21:39:48 -0700
commit5965a434d0923738d49334eb5f3d74a259e7b431 (patch)
tree79f75c69c85e399a9ba9b5eac849962fdb0915bc /usrp2/fpga/top
parent43dec22f22e9c47b4f908675ac880a05377993fa (diff)
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seems to build a decent fpga, but still some issues with a full connection.
Diffstat (limited to 'usrp2/fpga/top')
-rwxr-xr-xusrp2/fpga/top/u2_core/u2_core.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 7fc2ce83b..a6596eb90 100755
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -588,7 +588,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
-
+/*
serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
@@ -598,7 +598,7 @@ module u2_core
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
-
+*/
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
@@ -659,7 +659,7 @@ module u2_core
eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
- assign debug_clk[0] = wb_clk;
+ assign debug_clk[0] = 0; // wb_clk;
assign debug_clk[1] = clk_to_mac;
/*