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authorMatt Ettus2009-09-29 22:35:38 -0700
committerMatt Ettus2009-09-29 22:35:38 -0700
commite5b76a1b9239f560b3aad21d56a7b417f3c8b0b5 (patch)
tree44f07bbd02110e0d3e694d37cbffc04cfd683f53 /usrp2/fpga/timing/time_sync.v
parentc88f64ad42a8473a1749275c0e579284b20eb283 (diff)
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Enable pps interrupts. Not sure why they were disabled in the first place.
Diffstat (limited to 'usrp2/fpga/timing/time_sync.v')
-rw-r--r--usrp2/fpga/timing/time_sync.v5
1 files changed, 2 insertions, 3 deletions
diff --git a/usrp2/fpga/timing/time_sync.v b/usrp2/fpga/timing/time_sync.v
index a4c021f58..c0c8e195f 100644
--- a/usrp2/fpga/timing/time_sync.v
+++ b/usrp2/fpga/timing/time_sync.v
@@ -133,12 +133,11 @@ module time_sync
always @(posedge wb_clk_i)
if(rst_i)
int_o <= 0;
-/*
- else if(tick_int_enable & (internal_tick | internal_tick_d1))
+ else if(tick_int_enable & (internal_tick | internal_tick_d1))
int_o <= 1;
else
int_o <= 0;
-*/
+
always @(posedge sys_clk_i)
if(rst_i)
epoch_o <= 0;