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| author | Matt Ettus | 2009-10-01 00:21:24 -0700 |
|---|---|---|
| committer | Matt Ettus | 2009-10-01 00:21:24 -0700 |
| commit | 21e931766545ff93dda5ef1b72dd03f3786967ab (patch) | |
| tree | 4b337a566c42e879414d4a2bf92fa577cca88b77 /usrp2/fpga/testbench/cmdfile | |
| parent | 413d26237e93b8b019c719ed186e228a8eeb41b8 (diff) | |
| download | gnuradio-21e931766545ff93dda5ef1b72dd03f3786967ab.tar.gz gnuradio-21e931766545ff93dda5ef1b72dd03f3786967ab.tar.bz2 gnuradio-21e931766545ff93dda5ef1b72dd03f3786967ab.zip | |
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
Diffstat (limited to 'usrp2/fpga/testbench/cmdfile')
| -rw-r--r-- | usrp2/fpga/testbench/cmdfile | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile index ed251665c..8083eb92a 100644 --- a/usrp2/fpga/testbench/cmdfile +++ b/usrp2/fpga/testbench/cmdfile @@ -9,6 +9,8 @@ -y ../timing -y ../coregen -y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim # Models -y ../models @@ -18,24 +20,8 @@ -y ../opencores/8b10b -y ../opencores/spi/rtl/verilog +incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog -y ../opencores/i2c/rtl/verilog +incdir+../opencores/i2c/rtl/verilog -y ../opencores/aemb/rtl/verilog -y ../opencores/simple_pic/rtl -# Ethernet -+incdir+../eth/rtl/verilog --y ../eth/rtl/verilog --y ../eth/rtl/verilog/MAC_tx --y ../eth/rtl/verilog/MAC_rx --y ../eth/rtl/verilog/miim --y ../eth/rtl/verilog/TECH --y ../eth/rtl/verilog/TECH/xilinx --y ../eth/rtl/verilog/RMON --y ../eth --y ../eth/bench/verilog - -# Ethernet Models --y ../eth/bench/verilog |