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| author | jcorgan | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan | 2008-09-08 01:00:12 +0000 |
| commit | e0fcbaee124d3e8c4c11bdda662f88e082352058 (patch) | |
| tree | a51ef1c8b949681f45e5664478e8515065cfff5b /usrp2/fpga/testbench/BOOTSTRAP.sav | |
| parent | c86f6c23c6883f73d953d64c28ab42cedb77e4d7 (diff) | |
| download | gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.gz gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.bz2 gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga/testbench/BOOTSTRAP.sav')
| -rw-r--r-- | usrp2/fpga/testbench/BOOTSTRAP.sav | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/usrp2/fpga/testbench/BOOTSTRAP.sav b/usrp2/fpga/testbench/BOOTSTRAP.sav new file mode 100644 index 000000000..41501945f --- /dev/null +++ b/usrp2/fpga/testbench/BOOTSTRAP.sav @@ -0,0 +1,82 @@ +[size] 1400 971 +[pos] -1 -1 +*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +u2_sim_top.cpld_clk +u2_sim_top.cpld_detached +u2_sim_top.cpld_din +u2_sim_top.cpld_done +u2_sim_top.cpld_start +u2_sim_top.aux_clk +u2_sim_top.clk_fpga +u2_sim_top.clk_sel[1:0] +u2_sim_top.clk_en[1:0] +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.sysctrl.ram_loader_done_i +u2_sim_top.cpld_model.sclk +u2_sim_top.cpld_model.start +u2_sim_top.u2_basic.ram_loader.rst_i +u2_sim_top.sen_clk +u2_sim_top.sen_dac +u2_sim_top.sclk +@22 +u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] +u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] +@28 +u2_sim_top.u2_basic.shared_spi.wb_we_i +u2_sim_top.u2_basic.shared_spi.wb_stb_i +u2_sim_top.u2_basic.shared_spi.wb_ack_o +@22 +u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] +u2_sim_top.u2_basic.shared_spi.ctrl[13:0] +u2_sim_top.u2_basic.shared_spi.divider[15:0] +u2_sim_top.u2_basic.shared_spi.char_len[6:0] +u2_sim_top.u2_basic.shared_spi.ss[7:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] +u2_sim_top.u2_basic.shared_spi.rx[127:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_stb_i +u2_sim_top.u2_basic.control_lines.wb_we_i +@22 +u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] +u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_cyc_i +@22 +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.clock_ready +u2_sim_top.u2_basic.ram_loader.done_o +u2_sim_top.u2_basic.dsp_rst +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +@22 +u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] +@28 +u2_sim_top.u2_basic.aeMB.iwb_ack_i +u2_sim_top.u2_basic.ram_loader_done +@22 +u2_sim_top.u2_basic.iram_rd_adr[15:0] +u2_sim_top.u2_basic.iram_rd_dat[31:0] +@28 +u2_sim_top.u2_basic.iram_wr_we +u2_sim_top.u2_basic.iram_wr_stb +@22 +u2_sim_top.u2_basic.iram_wr_sel[3:0] +u2_sim_top.u2_basic.iram_wr_dat[31:0] +u2_sim_top.u2_basic.iram_wr_adr[15:0] +@28 +u2_sim_top.u2_basic.ram_loader.ram_loader_done_o +u2_sim_top.u2_basic.ID_ram.dwb_we_i +u2_sim_top.u2_basic.ID_ram.iwb_we_i +u2_sim_top.u2_basic.ram_loader.ram_we +u2_sim_top.u2_basic.ram_loader.ram_we_q +u2_sim_top.u2_basic.ram_loader.ram_we_s +u2_sim_top.u2_basic.ram_loader.wb_ack_i +u2_sim_top.u2_basic.ID_ram.iwb_ack_o +u2_sim_top.u2_basic.ID_ram.iwb_stb_i +u2_sim_top.u2_basic.ID_ram.wb_rst_i |