diff options
| author | Johnathan Corgan | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/testbench/BOOTSTRAP.sav | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
| download | gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.tar.gz gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.tar.bz2 gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.zip | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/testbench/BOOTSTRAP.sav')
| -rw-r--r-- | usrp2/fpga/testbench/BOOTSTRAP.sav | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/usrp2/fpga/testbench/BOOTSTRAP.sav b/usrp2/fpga/testbench/BOOTSTRAP.sav deleted file mode 100644 index 41501945f..000000000 --- a/usrp2/fpga/testbench/BOOTSTRAP.sav +++ /dev/null @@ -1,82 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.cpld_clk -u2_sim_top.cpld_detached -u2_sim_top.cpld_din -u2_sim_top.cpld_done -u2_sim_top.cpld_start -u2_sim_top.aux_clk -u2_sim_top.clk_fpga -u2_sim_top.clk_sel[1:0] -u2_sim_top.clk_en[1:0] -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.ram_loader_done_i -u2_sim_top.cpld_model.sclk -u2_sim_top.cpld_model.start -u2_sim_top.u2_basic.ram_loader.rst_i -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.sclk -@22 -u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] -u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] -@28 -u2_sim_top.u2_basic.shared_spi.wb_we_i -u2_sim_top.u2_basic.shared_spi.wb_stb_i -u2_sim_top.u2_basic.shared_spi.wb_ack_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] -u2_sim_top.u2_basic.shared_spi.ctrl[13:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -u2_sim_top.u2_basic.shared_spi.char_len[6:0] -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] -u2_sim_top.u2_basic.shared_spi.rx[127:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -@22 -u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] -u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_cyc_i -@22 -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.clock_ready -u2_sim_top.u2_basic.ram_loader.done_o -u2_sim_top.u2_basic.dsp_rst -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -@22 -u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] -@28 -u2_sim_top.u2_basic.aeMB.iwb_ack_i -u2_sim_top.u2_basic.ram_loader_done -@22 -u2_sim_top.u2_basic.iram_rd_adr[15:0] -u2_sim_top.u2_basic.iram_rd_dat[31:0] -@28 -u2_sim_top.u2_basic.iram_wr_we -u2_sim_top.u2_basic.iram_wr_stb -@22 -u2_sim_top.u2_basic.iram_wr_sel[3:0] -u2_sim_top.u2_basic.iram_wr_dat[31:0] -u2_sim_top.u2_basic.iram_wr_adr[15:0] -@28 -u2_sim_top.u2_basic.ram_loader.ram_loader_done_o -u2_sim_top.u2_basic.ID_ram.dwb_we_i -u2_sim_top.u2_basic.ID_ram.iwb_we_i -u2_sim_top.u2_basic.ram_loader.ram_we -u2_sim_top.u2_basic.ram_loader.ram_we_q -u2_sim_top.u2_basic.ram_loader.ram_we_s -u2_sim_top.u2_basic.ram_loader.wb_ack_i -u2_sim_top.u2_basic.ID_ram.iwb_ack_o -u2_sim_top.u2_basic.ID_ram.iwb_stb_i -u2_sim_top.u2_basic.ID_ram.wb_rst_i |