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| author | Matt Ettus | 2009-09-04 16:43:11 -0700 |
|---|---|---|
| committer | Matt Ettus | 2009-09-04 16:43:11 -0700 |
| commit | 1048666fba8abf654c9abba84a849ba2d6885221 (patch) | |
| tree | b602dd8d33628eb1b4bd894b42af4e0c587b625b /usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | |
| parent | 1392a442651b9528537ca722df76090bbf4de0d9 (diff) | |
| download | gnuradio-1048666fba8abf654c9abba84a849ba2d6885221.tar.gz gnuradio-1048666fba8abf654c9abba84a849ba2d6885221.tar.bz2 gnuradio-1048666fba8abf654c9abba84a849ba2d6885221.zip | |
allow control of whether or not to honor flow control, adds some debug lines
Diffstat (limited to 'usrp2/fpga/simple_gemac/simple_gemac_wrapper.v')
| -rw-r--r-- | usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v index b9bc05848..8da77f096 100644 --- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v @@ -38,7 +38,7 @@ module simple_gemac_wrapper .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), + .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), @@ -136,9 +136,19 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - assign debug = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, - { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, - { tx_data} }; + wire [31:0] debug_tx, debug_rx; + + assign debug_tx = { { tx_ll_data }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, + tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, + { tx_data} }; + assign debug_rx = { { rx_ll_data }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, + rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, + { rx_data} }; + + assign debug = debug_rx; + endmodule // simple_gemac_wrapper |