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authorJohnathan Corgan2009-08-31 12:08:30 -0700
committerJohnathan Corgan2009-08-31 12:08:30 -0700
commit7eea883c377f64862a4d83f1b33a83fdf3cfc392 (patch)
tree2c4b4d32c28e331cea42b16e001e89a74eb3b3e2 /usrp2/fpga/serdes/serdes.v
parent1aa216df204197b4849581dd4f42b2e7680eb72f (diff)
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Merged SVN matt/new_eth r10782:11633 into new_eth
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
Diffstat (limited to 'usrp2/fpga/serdes/serdes.v')
-rw-r--r--usrp2/fpga/serdes/serdes.v16
1 files changed, 6 insertions, 10 deletions
diff --git a/usrp2/fpga/serdes/serdes.v b/usrp2/fpga/serdes/serdes.v
index 8429b8fd9..17049bfe6 100644
--- a/usrp2/fpga/serdes/serdes.v
+++ b/usrp2/fpga/serdes/serdes.v
@@ -7,12 +7,10 @@ module serdes
(input clk, input rst,
// TX side
output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb,
- input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
- input rd_sop_i, input rd_eop_i,
+ input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i,
// RX side
input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
- output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
- input wr_ready_i, input wr_full_i,
+ output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i,
output [15:0] tx_occupied, output tx_full, output tx_empty,
output [15:0] rx_occupied, output rx_full, output rx_empty,
@@ -29,8 +27,7 @@ module serdes
serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
(.clk(clk),.rst(rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
- .rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
- .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
+ .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i),
.inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent),
.fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
.debug(debug_tx) );
@@ -38,8 +35,7 @@ module serdes
serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
(.clk(clk),.rst(rst),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
- .wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o),
- .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
+ .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i),
.fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
.fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
.serdes_link_up(serdes_link_up), .debug(debug_rx) );
@@ -55,13 +51,13 @@ module serdes
//assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
//assign debug = debug_rx;
- assign debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, rd_read_o, rd_done_o, rd_sop_i, rd_eop_i },
+ assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]},
{ debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
{ ser_t[15:8] },
{ ser_t[7:0] } };
assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
- { wr_write_o, wr_error_o, wr_ready_i, wr_done_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
+ { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
{ ser_r[15:8] },
{ ser_r[7:0] } };
endmodule // serdes