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author | jcorgan | 2008-09-08 01:00:12 +0000 |
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committer | jcorgan | 2008-09-08 01:00:12 +0000 |
commit | e0fcbaee124d3e8c4c11bdda662f88e082352058 (patch) | |
tree | a51ef1c8b949681f45e5664478e8515065cfff5b /usrp2/fpga/sdr_lib/dummy_rx.v | |
parent | c86f6c23c6883f73d953d64c28ab42cedb77e4d7 (diff) | |
download | gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.gz gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.bz2 gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga/sdr_lib/dummy_rx.v')
-rw-r--r-- | usrp2/fpga/sdr_lib/dummy_rx.v | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/usrp2/fpga/sdr_lib/dummy_rx.v b/usrp2/fpga/sdr_lib/dummy_rx.v new file mode 100644 index 000000000..99290ecec --- /dev/null +++ b/usrp2/fpga/sdr_lib/dummy_rx.v @@ -0,0 +1,62 @@ + +`define DSP_CORE_RX_BASE 160 +module dummy_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + output [31:0] sample, + input run, + output strobe + ); + + wire [15:0] scale_i, scale_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [23:0] i_decim, q_decim; + wire [7:0] decim_rate; + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(decim_rate),.changed()); + + strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_in(1),.strobe(strobe) ); + + reg [15:0] i_out, q_out; + assign sample = {i_out,q_out}; + + always @(posedge clk) + if(rst) + i_out <= 0; + else if(~run) + i_out <= 0; + else if(strobe) + i_out <= i_out + 1; + + reg run_d1; + always @(posedge clk) + if(rst) + run_d1 <= 0; + else + run_d1 <= run; + + always @(posedge clk) + if(rst) + q_out <= 0; + else if (run & ~run_d1) + q_out <= q_out + 1; + + +endmodule // dsp_core_rx |