Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 17 deletions

diff --git a/usrp2/fpga/sdr_lib/add2_reg.v b/usrp2/fpga/sdr_lib/add2_reg.v
deleted file mode 100644
index 456cf315b..000000000
--- a/usrp2/fpga/sdr_lib/add2_reg.v
+++ /dev/null
@@ -1,17 +0,0 @@
-
-module add2_reg
-  #(parameter WIDTH=16)
-    (input clk,
-     input [WIDTH-1:0] in1,
-     input [WIDTH-1:0] in2,
-     output reg [WIDTH-1:0] sum);
-
-   wire [WIDTH-1:0] sum_int;
-   
-   add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int));
-
-   always @(posedge clk)
-     sum <= sum_int;
-   
-endmodule // add2_reg
-