Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 28 deletions

diff --git a/usrp2/fpga/sdr_lib/acc.v b/usrp2/fpga/sdr_lib/acc.v
deleted file mode 100644
index a2da9c86d..000000000
--- a/usrp2/fpga/sdr_lib/acc.v
+++ /dev/null
@@ -1,28 +0,0 @@
-
-module acc
-  #(parameter IWIDTH=16, OWIDTH=30)
-    (input clk,
-     input clear,
-     input acc,
-     input [IWIDTH-1:0] in,
-     output reg [OWIDTH-1:0] out);
-
-   wire [OWIDTH-1:0] in_signext;
-   sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 
-     acc_signext (.in(in),.out(in_signext));
-   
-   //  CLEAR & ~ACC  -->  clears the accumulator
-   //  CLEAR & ACC -->    loads the accumulator
-   //  ~CLEAR & ACC -->   accumulates
-   //  ~CLEAR & ~ACC -->  hold
-   
-   wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
-   wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
-   wire [OWIDTH-1:0] sum_int = addend1 + addend2;
-
-   always @(posedge clk)
-     out <= sum_int;
-   
-endmodule // acc
-
-