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authorJohnathan Corgan2010-02-28 12:47:43 -0800
committerJohnathan Corgan2010-02-28 12:47:43 -0800
commita2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch)
tree77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/opencores/aemb/sim/iversim
parentdb29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff)
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Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/opencores/aemb/sim/iversim')
-rwxr-xr-xusrp2/fpga/opencores/aemb/sim/iversim21
1 files changed, 0 insertions, 21 deletions
diff --git a/usrp2/fpga/opencores/aemb/sim/iversim b/usrp2/fpga/opencores/aemb/sim/iversim
deleted file mode 100755
index 9d2384b5a..000000000
--- a/usrp2/fpga/opencores/aemb/sim/iversim
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh
-# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
-# $Log: iversim,v $
-# Revision 1.5 2007/12/11 00:44:30 sybreon
-# Modified for AEMB2
-#
-# Revision 1.4 2007/11/30 17:08:30 sybreon
-# Moved simulation kernel into code.
-#
-# Revision 1.3 2007/11/09 20:50:51 sybreon
-# Added log output to iverilog.log
-#
-# Revision 1.2 2007/11/05 10:59:31 sybreon
-# Added random seed for simulation.
-#
-# Revision 1.1 2007/03/09 17:41:55 sybreon
-# initial import
-#
-RANDOM=$(date +%s)
-echo "parameter randseed = $RANDOM;" > random.v
-iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out