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| author | jcorgan | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan | 2008-09-08 01:00:12 +0000 |
| commit | e0fcbaee124d3e8c4c11bdda662f88e082352058 (patch) | |
| tree | a51ef1c8b949681f45e5664478e8515065cfff5b /usrp2/fpga/models/CY7C1356C/readme.txt | |
| parent | c86f6c23c6883f73d953d64c28ab42cedb77e4d7 (diff) | |
| download | gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.gz gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.bz2 gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga/models/CY7C1356C/readme.txt')
| -rw-r--r-- | usrp2/fpga/models/CY7C1356C/readme.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/usrp2/fpga/models/CY7C1356C/readme.txt b/usrp2/fpga/models/CY7C1356C/readme.txt new file mode 100644 index 000000000..3578c80dc --- /dev/null +++ b/usrp2/fpga/models/CY7C1356C/readme.txt @@ -0,0 +1,33 @@ +***************************
+Cypress Semiconductor
+MPD Applications
+Verilog model for NoBL SRAM CY7C1356
+Created: August 04, 2004
+Rev: 1.0
+***************************
+
+This is the verilog model for the CY7C1356 along with the testbench and test vectors.
+
+Contact support@cypress.com if you have any questions.
+
+This directory has 4 files. including this readme.
+
+1)cy7c1356c.v -> Verilog model for CY7C1356c
+
+2)cy1356.inp -> Test Vector File used for testing the verilog model
+
+3)testbench.v -> Test bench used for testing the verilog model
+
+
+COMPILING METHOD :
+------------------
+
+ verilog +define+<speed_bin> <Main File> <Test bench File>
+
+ Ex:
+ verilog +define+sb133 CY7C1356c.v testbench.v
+
+VERIFIED WITH:
+--------------
+
+VERILOG-XL 2.2
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