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authorMatt Ettus2009-09-05 13:38:13 -0700
committerMatt Ettus2009-09-05 13:38:13 -0700
commitdb03fafeec9d360a9837303befcc2dbcce57a06b (patch)
treee436f1a29abb3917bf05c6e5f255df48bf5bf32f /usrp2/fpga/eth/rtl/verilog/eth_miim.v
parent9e05f0770b92f9c85f09e3629f875011e8f1ac24 (diff)
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fix a typo which caused tx glitches
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