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author | jcorgan | 2008-09-08 01:00:12 +0000 |
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committer | jcorgan | 2008-09-08 01:00:12 +0000 |
commit | e0fcbaee124d3e8c4c11bdda662f88e082352058 (patch) | |
tree | a51ef1c8b949681f45e5664478e8515065cfff5b /usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v | |
parent | c86f6c23c6883f73d953d64c28ab42cedb77e4d7 (diff) | |
download | gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.gz gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.tar.bz2 gnuradio-e0fcbaee124d3e8c4c11bdda662f88e082352058.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v')
-rw-r--r-- | usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v b/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v new file mode 100644 index 000000000..757049ec4 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v @@ -0,0 +1,66 @@ + +module elastic_buffer_tb; + + reg rx_clk = 0, tx_clk = 0, rst = 1; + + reg [7:0] rxd; + wire [7:0] rxd_ret; + reg rx_dv, rx_er, crs, col; + wire rx_dv_ret, rx_er_ret, crs_ret, col_ret; + + elastic_buffer elastic_buffer + (.rx_clk(rx_clk),.tx_clk(tx_clk),.rst(rst), + .rxd(rxd),.rx_dv(rx_dv),.rx_er(rx_er),.crs(crs),.col(col), + .rxd_ret(rxd_ret),.rx_dv_ret(rx_dv_ret),.rx_er_ret(rx_er_ret), + .crs_ret(crs_ret),.col_ret(col_ret) ); + + always #100 rx_clk = ~rx_clk; + always #101 tx_clk = ~tx_clk; + initial #950 rst = 0; + + initial + begin + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(negedge rst); + @(posedge rx_clk); + + repeat (13) + begin + repeat (284) + @(posedge rx_clk); + SendPKT; + end + repeat (100) + @(posedge rx_clk); + $finish; + end // initial begin + + reg [7:0] rxd_ret_d1; + always @(posedge tx_clk) + rxd_ret_d1 <= rxd_ret; + + wire [7:0] diff = rxd_ret_d1 - rxd_ret; + + wire error = rx_dv_ret && (diff != 8'hFF); + + task SendPKT; + begin + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(posedge rx_clk); + {col,crs,rx_er,rx_dv,rxd} <= {4'hF,8'd1}; + @(posedge rx_clk); + repeat (250) + begin + rxd <= rxd + 1; + @(posedge rx_clk); + end + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(posedge rx_clk); + end + endtask // SendPKT + + initial begin + $dumpfile("elastic_buffer_tb.vcd"); + $dumpvars(0,elastic_buffer_tb); + end +endmodule // elastic_buffer_tb |