timing fix, delays the ethernet flow control by a cycle to get it across the chip. Seems ok in testing.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10523 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 9 insertions, 1 deletions

diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
index 0fd7c603e..8da2e253c 100644
--- a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
@@ -627,7 +627,15 @@ always @ (posedge Clk or posedge Reset)
         pause_quanta_sub    <=0;

 

 // FIXME  The below probably won't work if the pause request comes when we are in the wrong state

-   wire clear_xonxoff = (Current_state==StateSendPauseFrame) & (IPLengthCounter==17);

+   reg clear_xonxoff;

+   always @(posedge Clk or posedge Reset)

+     if(Reset)

+       clear_xonxoff <= 0;

+     else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17))

+       clear_xonxoff <= 1;

+     else if(~xon_gen & ~xoff_gen)

+       clear_xonxoff <= 0;

+   

 always @ (posedge Clk or posedge Reset)

     if (Reset) 

         xoff_gen_complete   <=0;