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| author | matt | 2009-02-26 04:42:33 +0000 |
|---|---|---|
| committer | matt | 2009-02-26 04:42:33 +0000 |
| commit | 8c0095f191a8db3994d7f6f6b49b868d1a49743b (patch) | |
| tree | 70d6eedeee2f6e7731f9ae55132b0f0f67627de3 /usrp2/fpga/eth/rtl/verilog/MAC_tx.v | |
| parent | 877bb0fb32b188f0eb7a697ace229d04653eff58 (diff) | |
| download | gnuradio-8c0095f191a8db3994d7f6f6b49b868d1a49743b.tar.gz gnuradio-8c0095f191a8db3994d7f6f6b49b868d1a49743b.tar.bz2 gnuradio-8c0095f191a8db3994d7f6f6b49b868d1a49743b.zip | |
timing fix, delays the ethernet flow control by a cycle to get it across the chip. Seems ok in testing.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10523 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga/eth/rtl/verilog/MAC_tx.v')
| -rw-r--r-- | usrp2/fpga/eth/rtl/verilog/MAC_tx.v | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v index 50b08dffb..bbf331022 100644 --- a/usrp2/fpga/eth/rtl/verilog/MAC_tx.v +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v @@ -127,6 +127,11 @@ wire MAC_tx_addr_init ; wire MAC_tx_addr_rd ;
wire[7:0] MAC_tx_addr_data ;
+
+ reg xon_gen_d1, xoff_gen_d1;
+ always @(posedge Clk) xon_gen_d1 <= xon_gen;
+ always @(posedge Clk) xoff_gen_d1 <= xoff_gen;
+
//******************************************************************************
//instantiation
//******************************************************************************
@@ -147,9 +152,9 @@ MAC_tx_ctrl U_MAC_tx_ctrl( //flow control (//flow control ),
.pause_apply (pause_apply ),
.pause_quanta_sub (pause_quanta_sub ),
-.xoff_gen (xoff_gen ),
+.xoff_gen (xoff_gen_d1 ),
.xoff_gen_complete (xoff_gen_complete ),
-.xon_gen (xon_gen ),
+.xon_gen (xon_gen_d1 ),
.xon_gen_complete (xon_gen_complete ),
//MAC_tx_FF (//MAC_tx_FF ),
.Fifo_data (Fifo_data ),
|