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authorJosh Blum2009-08-28 20:39:35 -0700
committerJosh Blum2009-08-28 20:39:35 -0700
commit5f7bd3f80387ea699649f76bd22d0be5ba08732d (patch)
tree0876a8bb0a10061a30fd321bbfcdbe58e52a0908 /usrp2/fpga/eth/bench/verilog/txmac.scr
parentcadc9548afb7b4a385cea51f48745f0a1c702607 (diff)
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avoid loops
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