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| author | Tom | 2009-10-06 10:40:39 -0700 |
|---|---|---|
| committer | Tom | 2009-10-06 10:40:39 -0700 |
| commit | bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef (patch) | |
| tree | dbf63fb638238e389ad970f2f4443299491e8fc6 /usrp2/fpga/eth/bench/verilog/test.scr | |
| parent | 314726ae7457b37f442a2751285b75b0d616c0f4 (diff) | |
| parent | 3f8026a00c261c788357b3a04f5b338a6cda4d0e (diff) | |
| download | gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.tar.gz gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.tar.bz2 gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.zip | |
Merge branch 'master' into sync
Conflicts:
gr-utils/src/python/gr_plot_qt.py
gr-utils/src/python/pyqt_plot.py
gr-utils/src/python/pyqt_plot.ui
Diffstat (limited to 'usrp2/fpga/eth/bench/verilog/test.scr')
| -rw-r--r-- | usrp2/fpga/eth/bench/verilog/test.scr | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/usrp2/fpga/eth/bench/verilog/test.scr b/usrp2/fpga/eth/bench/verilog/test.scr deleted file mode 100644 index 2ad127d31..000000000 --- a/usrp2/fpga/eth/bench/verilog/test.scr +++ /dev/null @@ -1,23 +0,0 @@ -// This tests just runs trough a couple of different packet lengths
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 320-byte frame 1 time - and expect it to be received again!
-20 01 40 00 01
-
-// Transmit a 80-byte frame 1 time - and expect it to be received again!
-20 00 50 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
|