Merge commit '38d5389f3054164a2f04d6e4e8fe381aa5ee03fc' into vrt

1 files changed, 0 insertions, 42 deletions

diff --git a/usrp2/fpga/eth/bench/verilog/files.lst b/usrp2/fpga/eth/bench/verilog/files.lst
deleted file mode 100644
index 6175a4d43..000000000
--- a/usrp2/fpga/eth/bench/verilog/files.lst
+++ /dev/null
@@ -1,42 +0,0 @@
-../../rtl/verilog/MAC_rx/Broadcast_filter.v

-../../rtl/verilog/MAC_rx/CRC_chk.v

-../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v

-../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v

-../../rtl/verilog/MAC_rx/MAC_rx_FF.v

-

-../../rtl/verilog/MAC_tx/CRC_gen.v

-../../rtl/verilog/MAC_tx/flow_ctrl.v

-../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v

-../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v

-../../rtl/verilog/MAC_tx/MAC_tx_FF.v

-../../rtl/verilog/MAC_tx/Ramdon_gen.v

-

-../../rtl/verilog/miim/eth_clockgen.v

-../../rtl/verilog/miim/eth_outputcontrol.v

-../../rtl/verilog/miim/eth_shiftreg.v

-

-../../rtl/verilog/RMON/RMON_addr_gen.v

-../../rtl/verilog/RMON/RMON_ctrl.v

-../../rtl/verilog/RMON/RMON_dpram.v

-

-../../rtl/verilog/TECH/duram.v

-../../rtl/verilog/TECH/eth_clk_div2.v

-../../rtl/verilog/TECH/eth_clk_switch.v

-

-../../rtl/verilog/TECH/xilinx/BUFGMUX.v

-../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v

-

-../../rtl/verilog/Clk_ctrl.v

-../../rtl/verilog/eth_miim.v

-../../rtl/verilog/MAC_rx.v

-../../rtl/verilog/MAC_top.v

-../../rtl/verilog/MAC_tx.v

-../../rtl/verilog/Phy_int.v

-../../rtl/verilog/Reg_int.v

-../../rtl/verilog/RMON.v

-

-../../bench/verilog/Phy_sim.v

-../../bench/verilog/User_int_sim.v

-../../bench/verilog/host_sim.v

-../../bench/verilog/xlnx_glbl.v

-../../bench/verilog/tb_top.v