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authorJosh Blum2009-08-28 18:15:49 -0700
committerJosh Blum2009-08-28 18:15:49 -0700
commitcadc9548afb7b4a385cea51f48745f0a1c702607 (patch)
treed5f14ba1cf7f680ce81f28a569ba6eb7ec1c6ca6 /usrp2/fpga/eth/bench/verilog/Phy_sim.v
parent36d1520f0ac73b64bd0541b422552a6d419c7ffd (diff)
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Recursive resolution of virtual sources.
Flow graph generation code working. Also, mod to fft window to use clean/nice Db/div.
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