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authorJohnathan Corgan2009-08-31 12:08:30 -0700
committerJohnathan Corgan2009-08-31 12:08:30 -0700
commit7eea883c377f64862a4d83f1b33a83fdf3cfc392 (patch)
tree2c4b4d32c28e331cea42b16e001e89a74eb3b3e2 /usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
parent1aa216df204197b4849581dd4f42b2e7680eb72f (diff)
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Merged SVN matt/new_eth r10782:11633 into new_eth
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
Diffstat (limited to 'usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v')
-rw-r--r--usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v27
1 files changed, 27 insertions, 0 deletions
diff --git a/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v b/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
new file mode 100644
index 000000000..2abbbf3b5
--- /dev/null
+++ b/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
@@ -0,0 +1,27 @@
+
+module cascadefifo_2clock
+ #(parameter DWIDTH=32, AWIDTH=9)
+ (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
+ input arst);
+
+ wire [DWIDTH-1:0] data_int1, data_int2;
+ wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+
+ fifo_short #(.WIDTH(DWIDTH)) shortfifo
+ (.clk(wclk), .reset(arst), .clear(0),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
+
+ newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+ (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
+ .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+ .arst(arst) );
+
+ fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+ (.clk(rclk), .reset(arst), .clear(0),
+ .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
+
+endmodule // fifo_2clock_casc
+