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authorTom2009-10-06 10:40:39 -0700
committerTom2009-10-06 10:40:39 -0700
commitbbd3df51732b2b63ae9d20e9fddd12229cf6b2ef (patch)
treedbf63fb638238e389ad970f2f4443299491e8fc6 /usrp2/fpga/control_lib/fifo_writer.v
parent314726ae7457b37f442a2751285b75b0d616c0f4 (diff)
parent3f8026a00c261c788357b3a04f5b338a6cda4d0e (diff)
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Merge branch 'master' into sync
Conflicts: gr-utils/src/python/gr_plot_qt.py gr-utils/src/python/pyqt_plot.py gr-utils/src/python/pyqt_plot.ui
Diffstat (limited to 'usrp2/fpga/control_lib/fifo_writer.v')
-rw-r--r--usrp2/fpga/control_lib/fifo_writer.v31
1 files changed, 0 insertions, 31 deletions
diff --git a/usrp2/fpga/control_lib/fifo_writer.v b/usrp2/fpga/control_lib/fifo_writer.v
deleted file mode 100644
index 064ad3cb9..000000000
--- a/usrp2/fpga/control_lib/fifo_writer.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_writer
- #(parameter rate=4)
- (input clk,
- output [31:0] data_out,
- output write_o,
- input ready_i,
- input done_i
- );
-
- reg [7:0] state = 0;
-
-
- // FIXME change this to write
- always @(posedge clk)
- if(ready)
- if(state == rate)
- state <= 0;
- else
- state <= state + 1;
- else
- state <= 0;
-
- assign read = (state == rate);
-
- initial $monitor(data_in);
-
-endmodule // fifo_writer
-
-
-