Merge branch 'master' into sync

Conflicts:
	gr-utils/src/python/gr_plot_qt.py
	gr-utils/src/python/pyqt_plot.py
	gr-utils/src/python/pyqt_plot.ui

1 files changed, 2 insertions, 6 deletions

diff --git a/usrp2/fpga/control_lib/fifo_tb.v b/usrp2/fpga/control_lib/fifo_tb.v
index 98fd63f8d..616fe4ee7 100644
--- a/usrp2/fpga/control_lib/fifo_tb.v
+++ b/usrp2/fpga/control_lib/fifo_tb.v
@@ -2,11 +2,11 @@ module fifo_tb();
    
    reg clk, rst;
    wire short_full, short_empty, long_full, long_empty;
-   wire casc_full, casc_empty, casc2_full, casc2_empty;
+   wire casc2_full, casc2_empty;
    reg 	read, write;
    
    wire [7:0] short_do, long_do;
-   wire [7:0] casc_do, casc2_do;
+   wire [7:0] casc2_do;
    reg [7:0]  di;
 
    reg 	      clear = 0;
@@ -19,10 +19,6 @@ module fifo_tb();
      (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
       .read(read),.write(write),.full(long_full),.empty(long_empty));
    
-   cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
-      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-   
    cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
      (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
       .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));