Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 18 deletions

diff --git a/usrp2/fpga/control_lib/cmdfile b/usrp2/fpga/control_lib/cmdfile
deleted file mode 100644
index cb3756cfc..000000000
--- a/usrp2/fpga/control_lib/cmdfile
+++ /dev/null
@@ -1,18 +0,0 @@
-# My stuff
--y .
--y ../u2_basic
--y ../control_lib
--y ../sdr_lib
-
-# Models
--y ../models
-
-# Open Cores
--y ../opencores/spi/rtl/verilog
-+incdir+../opencores/spi/rtl/verilog
--y ../opencores/wb_conbus/rtl/verilog
-+incdir+../opencores/wb_conbus/rtl/verilog
--y ../opencores/i2c/rtl/verilog
-+incdir+../opencores/i2c/rtl/verilog
--y ../opencores/aemb/rtl/verilog
--y ../opencores/simple_gpio/rtl