Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth

* 'new_eth' of http://gnuradio.org/git/matt:
  properly set the address filter
  stop sending short ethernet command packets.
  Fix problem with commands timing out (specifically stop_rx_streaming)
  Fix race condition that caused commands such as stop_rx_streaming to fail.
  Fixing a line in the clock recovery algorithm. This works with a bit larger error than there proably should be.
  Better fix for broken AC_PROG_F77 macro
  Fix Python header check failure due to invalid cached state
  waterfall and fft use a common autoscale function
  Fix so that the waterfall texture is initialized with a buffer of the same size.
  Modifications to usrp2 source and sink so that set center freq is called afer set lo offset.
  Modifications to the usrp blocks and wrapper so that the lo offset is set with the lo frequency.
  Removed subversion related configuration info.
  Expand frequency ranges to match hardware capability.
  Modified log power fft block so ref scale is peak to peak.
  Adding clock sync algorithm using PFB. This works, but needs a bit more work.

3 files changed, 33 insertions, 46 deletions

diff --git a/usrp2/firmware/lib/db_rfx.c b/usrp2/firmware/lib/db_rfx.c
index 2f950016f..ff12f9e32 100644
--- a/usrp2/firmware/lib/db_rfx.c
+++ b/usrp2/firmware/lib/db_rfx.c
@@ -200,8 +200,8 @@ struct db_rfx_900_rx db_rfx_900_rx = {
   .base.is_tx = false,
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
-  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(800e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1000e6),
+  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(750e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1050e6),
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
@@ -231,8 +231,8 @@ struct db_rfx_900_tx db_rfx_900_tx = {
   .base.is_tx = true,
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
-  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(800e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1000e6),
+  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(750e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1050e6),
   //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
@@ -262,7 +262,7 @@ struct db_rfx_1200_rx db_rfx_1200_rx = {
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
   .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1350e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1450e6),
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
@@ -293,7 +293,7 @@ struct db_rfx_1200_tx db_rfx_1200_tx = {
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
   .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1350e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1450e6),
   //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
@@ -322,8 +322,8 @@ struct db_rfx_1800_rx db_rfx_1800_rx = {
   .base.is_tx = false,
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
-  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1600e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2000e6),
+  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1500e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2100e6),
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
@@ -353,8 +353,8 @@ struct db_rfx_1800_tx db_rfx_1800_tx = {
   .base.is_tx = true,
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
-  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1600e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2000e6),
+  .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1500e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2100e6),
   //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
@@ -385,7 +385,7 @@ struct db_rfx_2400_rx db_rfx_2400_rx = {
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
   .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2700e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2900e6),
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
@@ -416,7 +416,7 @@ struct db_rfx_2400_tx db_rfx_2400_tx = {
   .base.output_enables = 0x00E0,
   .base.used_pins = 0x00FF,
   .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
-  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2700e6),
+  .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2900e6),
   //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
   //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
diff --git a/usrp2/firmware/lib/eth_mac.c b/usrp2/firmware/lib/eth_mac.c
index f38ea65f9..becd93644 100644
--- a/usrp2/firmware/lib/eth_mac.c
+++ b/usrp2/firmware/lib/eth_mac.c
@@ -28,37 +28,15 @@
 void
 eth_mac_set_addr(const u2_mac_addr_t *src)
 {
-  int i;
-  eth_mac->ucast_hi = ((unsigned int)src->addr[0])<<8 + ((unsigned int)src->addr[1]);
-  eth_mac->ucast_lo = ((unsigned int)src->addr[2])<<24 + ((unsigned int)src->addr[3])<<16 +
-    ((unsigned int)src->addr[4])<<8 +((unsigned int)src->addr[5]);
-  
-  /*
-  // tell mac our source address and enable automatic insertion on Tx.
-  eth_mac->mac_tx_add_prom_wr = 0;	// just in case
-  for (i = 0; i < 6; i++){
-    eth_mac->mac_tx_add_prom_add = i;
-    eth_mac->mac_tx_add_prom_data = src->addr[i];
-    eth_mac->mac_tx_add_prom_wr = 1;
-    mdelay(1);
-    eth_mac->mac_tx_add_prom_wr = 0;
-    mdelay(1);
-  }
-  eth_mac->mac_tx_add_en = 1;  // overwrite pkt src addr field with this stuff
-
-  // set up receive destination address filter
-  eth_mac->mac_rx_add_prom_wr = 0;	// just in case
-  for (i = 0; i < 6; i++){
-    eth_mac->mac_rx_add_prom_add = i;
-    eth_mac->mac_rx_add_prom_data = src->addr[i];
-    eth_mac->mac_rx_add_prom_wr = 1;
-    mdelay(1);
-    eth_mac->mac_rx_add_prom_wr = 0;
-    mdelay(1);
-  }
-  // eth_mac->mac_rx_add_chk_en = 1;  // FIXME enable when everything's working
-
-  */
+  eth_mac->ucast_hi = 
+    (((unsigned int)src->addr[0])<<8) + 
+    ((unsigned int)src->addr[1]);
+  eth_mac->ucast_lo = 
+    (((unsigned int)src->addr[2])<<24) + 
+    (((unsigned int)src->addr[3])<<16) +
+    (((unsigned int)src->addr[4])<<8) +
+    (((unsigned int)src->addr[5]));
+  printf("RDBK %x:%x\n",eth_mac->ucast_hi,eth_mac->ucast_lo);
 }
 
 
@@ -68,7 +46,8 @@ eth_mac_init(const u2_mac_addr_t *src)
   eth_mac->miimoder = 25;	// divider from CPU clock (50MHz/25 = 2MHz)
 
   eth_mac_set_addr(src);
-  eth_mac->settings = 0x39; 
+  eth_mac->settings = MAC_SET_PAUSE_EN | MAC_SET_PASS_BCAST | MAC_SET_PASS_UCAST;  // 0x39; 
+
   // set rx flow control high and low water marks
   // unsigned int lwmark = (2*2048 + 64)/4; // 2 * 2048-byte frames + 1 * 64-byte pause frame
   // eth_mac->fc_hwmark = lwmark + 2048/4;  // plus a 2048-byte frame
@@ -119,7 +98,7 @@ eth_mac_miim_read(int addr)
     ;
 
   int r = eth_mac->miirx_data;
-  printf("MIIM-READ ADDR 0x%x DATA 0x%x\n",addr, r);
+  //printf("MIIM-READ ADDR 0x%x DATA 0x%x\n",addr, r);
   return r;
 }
 
@@ -131,7 +110,7 @@ eth_mac_miim_write(int addr, int value)
   eth_mac->miitx_data = value;
   eth_mac->miicommand = MIIC_WCTRLDATA;
 
-  printf("MIIM-WRITE ADDR 0x%x VAL 0x%x\n",addr,value);
+  //printf("MIIM-WRITE ADDR 0x%x VAL 0x%x\n",addr,value);
   while((eth_mac->miistatus & MIIS_BUSY) != 0)
     ;
 }
diff --git a/usrp2/firmware/lib/eth_mac_regs.h b/usrp2/firmware/lib/eth_mac_regs.h
index 3c866e471..a14c00641 100644
--- a/usrp2/firmware/lib/eth_mac_regs.h
+++ b/usrp2/firmware/lib/eth_mac_regs.h
@@ -37,6 +37,14 @@ typedef struct {
   volatile int miirx_data;
 } eth_mac_regs_t;
 
+// settings register
+#define MAC_SET_PAUSE_EN  (1 << 0)   // Makes us respect received pause frames (normally on)
+#define MAC_SET_PASS_ALL  (1 << 1)   // Enables promiscuous mode, currently broken
+#define MAC_SET_PASS_PAUSE (1 << 2)  // Sends pause frames through (normally off)
+#define MAC_SET_PASS_BCAST (1 << 3)  // Sends broadcast frames through (normally on)
+#define MAC_SET_PASS_MCAST (1 << 4)  // Sends multicast frames that match mcast addr (normally off)
+#define MAC_SET_PASS_UCAST (1 << 5)  // Sends unicast (normal) frames through if they hit in address filter (normally on)
+
 // miicommand register
 #define MIIC_SCANSSTAT	(1 << 0)	// Scan status
 #define MIIC_RSTAT      (1 << 1)	// Read status